MC68HC908EY16 Datasheet, PDF (58/278 Pages) Motorola, Inc – Microcontrollers

Configuration Registers (CONFIG1 and CONFIG2)
Address:
Read:
Write:
Reset:
$001F
Bit 7
COPRS
6
LVISTOP
5
LVIRSTD
4
3
LVIPWRD LVI5OR3⁽¹⁾
2
SSREC
1
STOP
0
0
0
0
0
0
0
1. The LVI5OR3 bit is cleared only by a power-on reset (POR).
Figure 5-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
ESCIBDSRC — ESCI Baud Rate Clock Source Bit
ESCIBDSRC controls the clock source used for the ESCI. The setting of the bit affects the frequency
at which the ESCI operates.
1 = Internal data bus clock used as clock source for ESCI
0 = CGMXCLK used as clock source for ESCI
EXTXTALEN — External Crystal Enable Bit
EXTXTALEN enables the external oscillator circuits to be configured for a crystal configuration where
the PTC4/OSC1 and PTC3/OSC2 pins are the connections for an external crystal.
NOTE
This bit does not function without setting the EXTCLKEN bit also.
Clearing the EXTXTALEN bit (default setting) allows the PTC3/OSC2 pin to function as a
general-purpose I/O pin. Refer to Table 5-1 for configuration options for the external source. See
Chapter 8 Internal Clock Generator (ICG) Module for a more detailed description of the external clock
operation.
Table 5-1. External Clock Option Settings
External Clock
Configuration Bits
Pin Function
EXTCLKEN EXTXTALEN PTC4/OSC1 PTC3/OSC2
Description
0
0
PTC4
PTC3 Default setting — external oscillator disabled
0
1
PTC4
PTC3 External oscillator disabled since EXTCLKEN not set
1
0
OSC1
PTC3
External oscillator configured for an external clock
source input (square wave) on OSC1
External oscillator configured for an external crystal
1
1
OSC1
OSC2 configuration on OSC1 and OSC2. System will also
operate with square-wave clock source in OSC1.
EXTXTALEN, when set, also configures the clock monitor to expect an external clock source in the
valid range of crystals (30 kHz to 100 kHz or 1 MHz to 8 MHz). When EXTXTALEN is clear, the clock
monitor will expect an external clock source in the valid range for externally generated clocks when
using the clock monitor (60 Hz to 32 MHz).
EXTXTALEN, when set, also configures the external clock stabilization divider in the clock monitor for
a 4096-cycle timeout to allow the proper stabilization time for a crystal. When EXTXTALEN is clear,
the stabilization divider is configured to 16 cycles since an external clock source does not need a
startup time.
1 = Allows PTC3/OSC2 to be an external crystal connection.
0 = PTC3/OSC2 functions as an I/O port pin (default).
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
58
Freescale Semiconductor