MC68HC908EY16 Datasheet, PDF (155/278 Pages) Motorola, Inc – Microcontrollers

Chapter 14
System Integration Module (SIM)
14.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. The SIM is a system state controller that coordinates the central processor unit (CPU)
and exception timing. Together with the CPU, the SIM controls all microcontroller unit (MCU) activities. A
block diagram of the SIM is shown in Figure 14-1.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Table 14-1 shows the internal signal names used in this section.
Table 14-1. Signal Name Conventions
Signal Name
CGMXCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
Description
Selected clock source from internal clock generator module (ICG)
Clock output from ICG module (bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset (POR) module to the SIM
Internal reset signal
Read/write signal
14.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 14-2. This clock
originates from either an external oscillator or from the internal clock generator.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
155