MC68HC908EY16 Datasheet, PDF (61/278 Pages) Motorola, Inc – Microcontrollers

Chapter 6
Computer Operating Properly (COP) Module
6.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if
allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset
by periodically clearing the COP counter.
6.2 Functional Description
BUSCLKX4
SIM MODULE
12-BIT SIM COUNTER
SIM RESET CIRCUIT
RESET STATUS REGISTER
INTERNAL RESET SOURCES⁽¹⁾
RESET VECTOR FETCH
COPCTL WRITE
COP CLOCK
COPEN (FROM SIM)
COPD (FROM CONFIG1)
RESET
COPCTL WRITE
COP RATE SELECT
(COPRS FROM CONFIG1)
COP MODULE
6-BIT COP COUNTER
CLEAR
COP COUNTER
1. See Chapter 14 System Integration Module (SIM) for more details.
Figure 6-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler. If not cleared by software,
the COP counter overflows and generates an asynchronous reset after 8176 or 262,128 CGMXCLK
cycles, depending on the state of the COP rate select bit, COPRS, in the CONFIG-1. When COPRS = 0,
a 4.9152-MHz crystal gives a COP timeout period of 53.3 ms. Writing any value to location $FFFF before
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
61