MC68HC908EY16 Datasheet, PDF (227/278 Pages) Motorola, Inc – Microcontrollers

ADDRESS BUS[15:8]
Break Module (BRK)
ADDRESS BUS[15:0]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
CONTROL
BKPT
(TO SIM)
ADDRESS BUS[7:0]
Figure 19-2. Break Module Block Diagram
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
CAUTION
A break address should be placed at the address of the instruction opcode.
When software does not change the break address and clears the BRKA
bit in the first break interrupt routine, the next break interrupt will not be
generated after exiting the interrupt routine even when the internal address
bus matches the value written in the break address registers.
19.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (SBFCR) enables software to clear status
bits during the break state. See 14.7.3 SIM Break Flag Control Register and the Break Interrupts
subsection for each module.
19.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
19.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt when V_TST is present on the RST pin.
19.2.2 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• Break status register (SBSR)
• Break flag control register (SBFCR)
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
227