MC68HC908EY16 Datasheet, PDF (86/278 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
CMON
EREF
IBASE
DLF MEASURE
OUTPUT CLOCK
ICGEN
FICGS
R
D
DFFRS
CK Q
S
CK Q
1/4
R
R
D
Q
DFFRR
CK
R
R
D
Q
DFFRR
CK
R
IOFF
ICGS
NAME
NAME
CONFIGURATION REGISTER BIT
NAME
REGISTER BIT
TOP LEVEL SIGNAL
NAME
MODULE SIGNAL
Figure 8-6. Internal Clock Activity Detector
8.3.4.3 External Clock Activity Detector
The external clock activity detector, shown in Figure 8-7, looks for at least one falling edge on the external
clock (ECLK) every time the internal reference (IREF) is low. Since IREF is less than half the frequency
of ECLK, this should occur every time. If it does not occur two consecutive times, the external clock
inactivity indicator (EOFF) is set. EOFF will be cleared the next time there is a falling edge of ECLK while
IREF is low.
The external clock stable bit (ECGS) is also generated in the external clock activity detector. ECGS is set
on a falling edge of the external stabilization clock (ESTBCLK). This will be 4096 ECLK cycles after the
external clock generator on bit is set, or the MCU exits stop mode (ECGEN = 1) if the external crystal
enable (EXTXTALEN) in the CONFIG is set, or 16 cycles when EXTXTALEN is clear. ECGS is cleared
when the external clock generator is turned off or in stop mode (ECGEN is clear) or when EOFF is set.
CMON
IREF
ECLK
R
D
DFFRS
CK Q
S
CK Q
1/4
R
R
D
DFFRR
CK Q
R
EOFF
EGGS
ESTBCLK
ECGEN
NAME
NAME
CONFIGURATION REGISTER BIT
NAME
REGISTER BIT
TOP LEVEL SIGNAL
NAME
MODULE SIGNAL
Figure 8-7. External Clock Activity Detector
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
86
Freescale Semiconductor