MC68HC908EY16 Datasheet, PDF (182/278 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI) Module
15.10 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
15.10.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction. In wait mode, the SPI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can
bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt
requests by setting the error interrupt enable bit (ERRIE). (See 15.7 Interrupts.)
15.10.2 Stop Mode
The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect register conditions. SPI operation resumes after the MCU exits stop mode. If stop mode is exited
by reset, any transfer in progress is aborted and the SPI is reset.
15.11 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR, $FE03) enables software to
clear status bits during the break state. (See 19.2.1.1 Flag Protection During Break Interrupts.)
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write I/O registers during the break state without affecting status bits. Some status
bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the
second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the data register
in break mode will not initiate a transmission nor will this data be transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.
15.12 I/O Signals
The SPI module has four I/O pins and shares three of them with a parallel I/O port.
• MISO — Data received
• MOSI — Data transmitted
• SPSCK — Serial clock
• SS — Slave select
• V_SS — Clock ground
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
182
Freescale Semiconductor