MC68HC908EY16 Datasheet, PDF (195/278 Pages) Motorola, Inc – Microcontrollers

Functional Description
INTERNAL
BUS CLOCK
PRESCALER
PRESCALER SELECT
TSTOP
TRST
16-BIT COUNTER
16-BIT COMPARATOR
TAMODH:TAMODL
CHANNEL 0
16-BIT COMPARATOR
TACH0H:TACH0L
16-BIT LATCH
CHANNEL 1
16-BIT COMPARATOR
TACH1H:TACH1L
16-BIT LATCH
PS2
PS1
PS0
TOF
TOIE
ELS0B ELS0A
CH0F
TOV0
CH0MAX
MS0A
ELS1B ELS1A
MS0B
CH1F
CH0IE
TOV1
CH1MAX
MS1A
CH1IE
Figure 17-2. TIMA Block Diagram
INTER-
RUPT
LOGIC
PTD0
LOGIC
INTER-
RUPT
LOGIC
PTD0/TACH0
PTD1
LOGIC
INTER-
RUPT
LOGIC
PTD1/TACH1
17.3.1 TIMA Counter Prescaler
The TIMA clock source can be one of the seven prescaler outputs. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMA status and control register
select the TIMA clock source.
17.3.2 Input Capture
An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit
counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value
of the free-running counter after the corresponding input capture edge detector senses a defined
transition. The polarity of the active edge is programmable. The level transition which triggers the counter
transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TASC0 through TASC1
control registers with x referring to the active channel number). When an active edge occurs on the pin of
an input capture channel, the TIMA latches the contents of the TIMA counter into the TIMA channel
registers, TACHxH–TACHxL. Input captures can generate TIMA CPU interrupt requests. Software can
determine that an input capture event has occurred by enabling input capture interrupts or by polling the
status flag bit.
The free-running counter contents are transferred to the TIMA channel status and control register
(TACHxH–TACHxL, see 17.8.5 TIMA Channel Registers) on each proper signal transition regardless of
whether the TIMA channel flag (CH0F–CH1F in TASC0–TASC1 registers) is set or clear. When the status
flag is set, a CPU interrupt is generated if enabled. The value of the count latched or “captured” is the time
of the event. Because this value is stored in the input capture register 2 bus cycles after the actual event
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
195