MC68HC908EY16 Datasheet, PDF (121/278 Pages) Motorola, Inc – Microcontrollers

Port D
Address: $0003
Bit 7
6
Read: 0
0
Write:
Reset:
Alternative Function:
5
4
3
2
1
Bit 0
0
0
0
0
PTD1
PTD0
Unaffected by reset
TACH1 TACH0
= Unimplemented
Figure 12-10. Port D Data Register (PTD)
PTD[1:0] — Port D Data Bits
PTD[1:0] are read/write, software programmable bits. Data direction of each port D pin is under the
control of the corresponding bit in data direction register D.
TACH[1:0] — Timer Channel I/O Bits
The PTD1/TACH1–PTD0/TACH0 pins are the TIMA input capture/output compare pins. The
edge/level select bits, ELSxB–ELSxA, determine whether the PTD1/TACH1–PTD0/TACH0 pins are
timer channel I/O pins or general-purpose I/O pins. See 17.8.1 TIMA Status and Control Register.
NOTE
Data direction register D (DDRD) does not affect the data direction of port
D pins that are being used by the TIMA. However, the DDRD bits always
determine whether reading port D returns the states of the latches or the
states of the pins. See Table 12-4.
12.5.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input or an output. Writing a 1 to a
DDRD bit enables the output buffer for the corresponding port D pin; a 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
6
5
4
3
2
1
0
0
0
0
0
0
DDRD1
0
0
0
0
0
0
0
= Unimplemented
Figure 12-11. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD[1:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD[1:0], configuring all port D pins
as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
121