MC68HC908EY16 Datasheet, PDF (29/278 Pages) Motorola, Inc – Microcontrollers

Input/Output (I/O) Section
Addr. Register Name
Bit 7
6
5
4
3
$0018
ESCII Arbiter Control Read:
ALOST
AFIN
Register
(SCIACTL)
Write:
AM1
AM0
ACLK
See page 151. Reset: 0
0
0
0
0
$0019
ESCI Arbiter Data Register ^Read:
(SCIACTL) Write:
See page 152. _Reset:
ARD7
0
ARD6
0
ARD5
0
ARD4
0
ARD3
0
Keyboard Status Read: 0
0
0
0
KEYF
$001A
and Control Register
(INTKBSCR)
Write:
See page 109. Reset: 0
0
0
0
0
Keyboard Interrupt Enable ^Read:
0
0
0
KBIE4
KBIE3
$001B
Register (INTKBIER) Write:
See page 110. _Reset:
0
0
0
0
0
Read: TBIF
$001C
Timebase Control Register
(TBCR)
Write:
See page 192. Reset: 0
TBR2
0
TBR1
0
TBR0
0
0
TACK
0
IRQ Status and Control ^Read:
0
0
0
0
IRQF
$001D
Register (INTSCR) Write:
See page 104. _Reset:
0
0
0
0
0
Read:
$001E
Configuration Register 2 _Write:
(CONFIG2)
R
See page 57. Reset: 0
ESCI
BDSRC
0
EXT-
XTALEN
0
EXT-
SLOW
0
EXT-
CLKEN
0
$001F
Configuration Register 1 ^Read:
(CONFIG1) Write:
See page 58. _Reset:
COPRS
0
LVISTOP LVIRSTD LVIPWRD LVI5OR3⁽¹⁾
0
0
0
0
1. The LVI5OR3 bit is cleared only by a power-on reset (POR).
Timer A Status and Control ^{Read: TOF}
TOIE TSTOP
0
R
$0020
Register (TASC) Write: 0
TRST
See page 201. _Reset:
0
0
1
0
0
$0021
Timer A Counter Register ^Read:
High (TACNTH) Write:
See page 203. _Reset:
BIT 15
0
BIT 14
0
BIT 13
0
BIT 12
0
BIT 11
0
Timer A Counter Register ^{Read: BIT 7}
BIT 6
BIT 5
BIT 4
BIT 3
$0022
Low (TACNTL) Write:
See page 203. _Reset:
0
0
0
0
0
= Unimplemented
R = Reserved
2
ARUN
1
AROVFL
0
ARD2
0
ARD1
0
0
ACKK
0
0
IMASKK
0
KBIE2 KBIE1
0
0
TBIE
TBON
0
0
0
IMASK
ACK
0
0
TMB- OSCENIN-
CLKSEL STOP
0
0
SSREC STOP
0
0
PS2
PS1
0
0
BIT 10
BIT 9
0
0
BIT 2
BIT 1
0
0
U = Unaffected
Bit 0
ARD8
0
ARD0
0
MODEK
0
KBIE0
0
R
0
MODE
0
SSB-
PUENB
1
COPD
0
PS0
0
BIT 8
0
BIT 0
0
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 7)
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
29