MC68HC908EY16 Datasheet, PDF (148/278 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
PDS2–PDS0 — Prescaler Divisor Select Bits
These read/write bits select the prescaler divisor as shown in Table 13-9. Reset clears PDS2–PDS0.
NOTE
The setting of ‘000’ will bypass not only this prescaler but also the Prescaler
Divisor Fine Adjust (PDFA). It is not recommended to bypass the prescaler
while ENSCI is set, because the switching is not glitch free.
Table 13-9. ESCI Prescaler Division Ratio
PDS[2:1:0]
000
001
010
011
100
101
110
111
Prescaler Divisor (PD)
Bypass this prescaler
2
3
4
5
6
7
8
PSSB4–PSSB0 — Clock Insertion Select Bits
These read/write bits select the number of clocks inserted in each 32 output cycle frame to achieve
more timing resolution on the average prescaler frequency as shown in Table 13-10. Reset clears
PSSB4–PSSB0.
Use the following formula to calculate the ESCI baud rate:
Frequency of the SCI clock source
Baud rate = _{64 x BPD x BD x (PD + PDFA)}
where:
Frequency of the SCI clock source = f_Bus or CGMXCLK (selected by
ESCIBDSRC in the CONFIG2 register)
BPD = Baud rate register prescaler divisor
BD = Baud rate divisor
PD = Prescaler divisor
PDFA = Prescaler divisor fine adjust
Table 13-11 shows the ESCI baud rates that can be generated with a 4.9152-MHz clock frequency.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
148
Freescale Semiconductor