MC68HC908EY16 Datasheet, PDF (59/278 Pages) Motorola, Inc – Microcontrollers

Functional Description
EXTSLOW — Slow External Crystal Enable Bit
The EXTSLOW bit has two functions. It configures the ICG module for a fast (1 MHz to 8 MHz) or slow
(30 kHz to 100 kHz) speed crystal. The option also configures the clock monitor operation in the ICG
module to expect an external frequency higher (307.2 kHz to 32 MHz) or lower (60 Hz to 307.2 kHz)
than the base frequency of the internal oscillator. See Chapter 8 Internal Clock Generator (ICG)
Module.
1 = ICG set for slow external crystal operation
0 = ICG set for fast external crystal operation
EXTCLKEN — External Clock Enable Bit
EXTCLKEN enables an external clock source or crystal/ceramic resonator to be used as a clock input.
Setting this bit enables PTC4/OSC1 pin to be a clock input pin. Clearing this bit (default setting) allows
the PTC4/OSC1 and PTC3/OSC2 pins to function as general-purpose input/output (I/O) pins. Refer to
Table 5-1 for configuration options for the external source. See Chapter 8 Internal Clock Generator
(ICG) Module for a more detailed description of the external clock operation.
1 = Allows PTC4/OSC1 to be an external clock connection
0 = PTC4/OSC1 and PTC3/OSC2 function as I/O port pins (default).
TMBCLKSEL — Timebase Clock Select Bit
TMBCLKSEL enables an enable the extra divide by 128 prescaler in the timebase module. Setting this
bit enables the extra prescaler and clearing this bit disables it. Refer to Table 16-1 for timebase divider
selection details.
1 = Enables extra divide by 128 prescaler in timebase module.
0 = Disables extra divide by 128 prescaler in timebase module.
OSCENINSTOP — Oscillator Enable In Stop Mode Bit
OSCENINSTOP, when set, will enable the internal clock generator module to continue to generate
clocks (either internal, ICLK, or external, ECLK) in stop mode. See Chapter 8 Internal Clock Generator
(ICG) Module. This function is used to keep the timebase running while the rest of the microcontroller
stops. When clear, all clock generation will cease and both ICLK and ECLK will be forced low during
stop mode. The default state for this option is clear, disabling the ICG in stop mode.
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
NOTE
This bit has the same functionality as the OSCSTOPENB CONFIG bit in
MC68HC908GP20 and MC68HC908GR8 parts.
SSBPUENB — SS Pullup Enable Bit
Clearing SSBPUENB enables the SS pullup resistor.
1 = Disables SS pullup resistor.
0 = Enables SS pullup resistor.
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. See Chapter 6 Computer Operating
Properly (COP) Module.
1 = COP timeout period = 8176 CGMXCLK cycles
0 = COP timeout period = 262,128 CGMXCLK cycles
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
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