MC68HC908EY16 Datasheet, PDF (111/278 Pages) Motorola, Inc – Microcontrollers

Chapter 11
Low-Voltage Inhibit (LVI) Module
11.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the V_DD pin
and can force a reset when the V_DD voltage falls to the LVI trip voltage.
11.2 Features
Features include:
• Programmable LVI reset
• Programmable power consumption
• 3 V or 5 V selectable trip point
11.3 Functional Description
Figure 11-1 shows the structure of the LVI module. The LVI is enabled out of reset. The following bits,
located in the configuration register, can alter the default conditions.
• Setting the LVI power disable bit, LVIPWRD, disables the LVI.
• Setting the LVI reset disable bit, LVIRSTD, prevents the LVI module from generating a reset.
• Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to continue monitoring the
voltage level on V_DD, while in stop mode.
V_DD
LVIPWRD
FROM CONFIG-1
LOW V_DD
DETECTOR
V_DD > LVI_TRIPR = 0
V_DD < LVI_TRIPF = 1
STOP INSTRUCTION
FROM CONFIG-1
LVIRSTD
LVISTOP
FROM CONFIG-1
LVI RESET
LVI5OR3
FROM CONFIG-1
LVIOUT
Figure 11-1. LVI Module Block Diagram
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
111