MC68HC908EY16 Datasheet, PDF (103/278 Pages) Motorola, Inc – Microcontrollers

FROM RESET
YES
I BIT SET?
NO
INTERRUPT?
NO
YES
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
IRQ Pin
FETCH NEXT
INSTRUCTION
SWI
YES
INSTRUCTION?
NO
RTI
YES
INSTRUCTION?
UNSTACK CPU REGISTERS
NO
EXECUTE INSTRUCTION
Figure 9-2. IRQ Interrupt Flowchart
If the MODE bit is clear, the IRQ pin is falling-edge sensitive only. With MODE clear, a vector fetch or
software clear immediately clears the IRQ latch.
The IRQF bit in the ISCR register can be used to check for pending interrupts. The IRQF bit is not affected
by the IMASK bit, which makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
103