MC68HC908EY16 Datasheet, PDF (92/278 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
• When DSTG[7:5] is %111, similar results are achieved by including a variable divide-by-two, so the
ring operates at 31 stages for some cycles and at 17 stage delays, with a divide-by-two for an
effective 34 stage delays, for the remainder of the cycles.
Adjusting the DSTG[0] bit has a 0.202 percent to 0.368 percent effect on the output clock period. This
corresponds to the minimum size correction made by the DLF, and the inherent, long-term quantization
error in the output frequency.
8.4.5 Switching Internal Clock Frequencies
The frequency of the internal clock (ICLK) may need to be changed for some applications. For example,
if the reset condition does not provide the correct frequency, or if the clock is slowed down for a low-power
mode (or sped up after a low-power mode), the frequency must be changed by programming the internal
clock multiplier factor (N). The frequency of ICLK is N times the frequency of IBASE, which is 307.2 kHz
±25 percent.
Before switching frequencies by changing the N value, the clock monitor must be disabled. This is
because when N is changed, the frequency of the low-frequency base clock (IBASE) will change
proportionally until the digital loop filter has corrected the error. Since the clock monitor uses IBASE, it
could erroneously detect an inactive clock. The clock monitor cannot be re-enabled until the internal clock
is stable again (ICGS is set).
The following flow is an example of how to change the clock frequency:
• Verify there is no clock monitor interrupt by reading the CMF bit.
• Turn off the clock monitor.
• If desired, switch to the external clock (see 8.4.1 Switching Clock Sources).
• Change the value of N.
• Switch back to internal (see 8.4.1 Switching Clock Sources),
if desired.
• Turn on the clock monitor (see 8.4.2 Enabling the Clock Monitor), if desired.
8.4.6 Nominal Frequency Settling Time
Because the clock period of the internal clock (ICLK) is dependent on the digital loop filter outputs (DDIV
and DSTG) which cannot change instantaneously, ICLK temporarily will operate at an incorrect clock
period when any operating condition changes. This happens whenever the part is reset, the ICG multiply
factor (N) is changed, the ICG trim factor (TRIM) is changed, or the internal clock is enabled after inactivity
(stop mode or disabled operation). The time that the ICLK takes to adjust to the correct period is known
as the settling time.
Settling time depends primarily on how many corrections it takes to change the clock period and the
period of each correction. Since the corrections require four periods of the low-frequency base clock
(4*τ_IBASE), and since ICLK is N (the ICG multiply factor for the desired frequency) times faster than
IBASE, each correction takes 4*N*τ_ICLK. The period of ICLK, however, will vary as the corrections occur.
8.4.6.1 Settling to Within 15 Percent
When the error is greater than 15 percent, the filter takes eight corrections to double or halve the clock
period. Due to how the DCO increases or decreases the clock period, the total period of these eight
corrections is approximately 11 times the period of the fastest correction. (If the corrections were perfectly
linear, the total period would be 11.5 times the minimum period; however, the ring must be slightly
nonlinear.) Therefore, the total time it takes to double or halve the clock period is 44*N*τ_ICLKFAST.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
92
Freescale Semiconductor