MC68HC908EY16 Datasheet, PDF (272/278 Pages) Motorola, Inc – Microcontrollers

Revision History
Changes from Rev 4.0 published in February 2003 to Rev 5.0 published in September 2003
Section
Throughout
Memory
Computer Operating
Properly (COP) Module
System Integration
Module (SIM)
Development Support
Electrical Specifications
Page (in Rev 5.0)
N/A
39
40
69
196
263
289
Description of change
Reformatted document to current publications standards
Updated procedures for FLASH page erase operation
Updated procedures for FLASH mass erase operation
Updated block diagram
Updated definition for SBSW bit of SIM break status register (SBSR)
Updated definition for SBSW bit of SIM break status register (SBSR)
Updated memory characteristics table with new information
Corrected notes to supply currents in 20.5 DC Electrical Characteristics.
Changes from Rev 3.0 published in November 2002 to Rev 4.0 published in February 2003
Section
Electrical
Specifications
Page (in Rev 4.0)
280
281
285
Description of change
Updated parameters for output high voltage (V_OH), output low voltage (V_OL)
and supply current (I_DD)
Updated parameters for low voltage inhibit reset: V_TRIPF, V_TRIPR and V_HYS.
Updated parameters for ADC absolute accuracy, zero input reading, full-scale
reading, zero input reading (8-bit truncated mode) and full-scale reading
(8-bit truncated mode).
Changes from Rev 2.0 published in May 2002 to Rev 3.0 published in November 2002
Section
Memory Map
FLASH Memory
System Integration
Module (SIM)
Internal Clock
Generator (ICG)
Module
Configuration Registers
(CONFIG1 &
CONFIG2)
Break Module (BRK)
Computer Operating
Properly (COP) Module
Low-Voltage Inhibit
(LVI) Module
External Interrupt (IRQ)
Page (in Rev 3.0)
50
56
62
93
94
106
118
137
151
148
152
162
178
179
180
181
183
190
191
Description of change
LVI5OR3 bit added to CONFIG1
ESCI vectors re-ordered
Minimum changed to 4ms in step 6.
Figure 6-5 updated
Figure 6-6 updated
Code example removed from SBSW description
PTB6/OSC1 and PTB7/OSC2 corrected to PTC4/OSC1 and PTC3/OSC2
respectively
COPD corrected to COPRS in COPRS bit description
LVI5OR3 bit added to CONFIG1 and default reset state changed to 0
LVI5OR3 description added
Code example removed from SBSW description
COPL corrected to COPRS in Figure 11-1
COPL corrected to COPRS in top paragraph
COPL corrected to COPRS in Section 11.4.8
IRQ1 corrected to IRQ
3rd bullet added to features
IRQ1 corrected to IRQ
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
272
Freescale Semiconductor