MC68HC908EY16 Datasheet, PDF (146/278 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
13.8.6 ESCI Data Register
The ESCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the ESCI data register.
Address: $0015
Bit 7
6
Read: R7
R6
Write: T7
T6
Reset:
5
4
3
2
R5
R4
R3
R2
T5
T4
T3
T2
Unaffected by Reset
1
Bit 0
R1
R0
T1
T0
Figure 13-15. ESCI Data Register (SCDR)
R7/T7:R0/T0 — Receive/Transmit Data Bits
Reading address $0015 accesses the read-only received data bits, R7:R0. Writing to address $0015
writes the data to be transmitted, T7:T0. Reset has no effect on the ESCI data register.
NOTE
Do not use read-modify-write instructions on the ESCI data register.
13.8.7 ESCI Baud Rate Register
The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for
both the receiver and the transmitter.
NOTE
There are two prescalers available to adjust the baud rate. One in the ESCI
baud rate register and one in the ESCI prescaler register.
Address:
Read:
Write:
Reset:
$0016
Bit 7
6
5
4
3
2
1
R
LINR
SCP1
SCP0
R
SCR2
SCR1
0
0
0
0
0
0
0
R
= Reserved
Figure 13-16. ESCI Baud Rate Register (SCBR)
Bit 0
SCR0
0
LINR — LIN Receiver Bit
This read/write bit selects the enhanced ESCI features for slave nodes in the local interconnect
network (LIN) protocol as shown in Table 13-6. Reset clears LINR.
Table 13-6. ESCI LIN Control Bits
LINR
0
1
1
M
Functionality
X Normal ESCI functionality
0 13-bit break detect enabled for LIN receiver
1 14-bit break detect enabled for LIN receiver
In LIN (version 1.2) systems, the master node transmits a break character which will appear as
11.05–14.95 dominant bits to the slave node. A data character of 0x00 sent from the master might
appear as 7.65–10.35 dominant bit times. This is due to the oscillator tolerance requirement that the
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
146
Freescale Semiconductor