MC68HC908EY16 Datasheet, PDF (112/278 Pages) Motorola, Inc – Microcontrollers

Low-Voltage Inhibit (LVI) Module
Once an LVI reset occurs, the MCU remains in reset until V_DD rises above a voltage, LVI_TRIPR. V_DD must
be above LVI_TRIPR for only one CPU cycle to bring the MCU out of reset (see 11.3.2 Forced Reset
Operation). The output of the comparator controls the state of the LVIOUT flag in the LVI status register
(LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
11.3.1 Polled LVI Operation
In applications that can operate at V_DD levels below the LVI_TRIPF level, software can monitor V_DD by
polling the LVIOUT bit. In the configuration register, the LVIPWRD bit must be at 0 to enable the LVI
module, and the LVIRSTD bit must be at 1 to disable LVI resets.
11.3.2 Forced Reset Operation
In applications that require V_DD to remain above the LVI_TRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when V_DD falls to the LVI_TRIPF level. In the configuration register, the LVIPWRD
and LVIRSTD bits must be at 0 to enable the LVI module and to enable LVI resets.
11.3.3 False Reset Protection
False reset protection is provided by the hysteresis in the LVI trip circuit (refer to Table 11-1). Please refer
to 20.5 DC Electrical Characteristics for hysteresis value (VHYS) and rising and falling LVI trip values.
11.3.4 LVI Status Register
The LVI status register flags V_DD voltages below the LVI_TRIPF level.
Address: $FE0C
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the LVI_TRIPF voltage. (See
Table 11-1.) Reset clears the LVIOUT bit.
Table 11-1. LVIOUT Bit Indication
V_DD
At Level:
V_DD > LVI_TRIPR
V_DD < LVI_TRIPF
LVI_TRIPF < V_DD < LVI_TRIPR
LVIOUT
0
1
Previous Value
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
112
Freescale Semiconductor