MC68HC908EY16 Datasheet, PDF (211/278 Pages) Motorola, Inc – Microcontrollers

Functional Description
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
TRST
16-BIT COUNTER
16-BIT COMPARATOR
TBMODH:TBMODL
CHANNEL 0
16-BIT COMPARATOR
TBCH0H:TBCH0L
16-BIT LATCH
CHANNEL 1
16-BIT COMPARATOR
TBCH1H:TBCH1L
16-BIT LATCH
PRESCALER SELECT
PS2
PS1
PS0
TOF
TOIE
ELS0B ELS0A
CH0F
TOV0
CH0MAX
MS0A
ELS1B ELS1A
MS0B
CH1F
CH0IE
TOV1
CH1MAX
MS1A
CH1IE
Figure 18-2. TIMB Block Diagram
INTERRUPT
LOGIC
PTB6
LOGIC
INTERRUPT
LOGIC
PTB6/TBCH0
PTB7
LOGIC
INTERRUPT
LOGIC
PTB7/TBCH1
18.3.1 TIMB Counter Prescaler
The TIMB clock source can be one of the seven prescaler outputs. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMB status and control register
select the TIMB clock source.
18.3.2 Input Capture
An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit
counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value
of the free-running counter after the corresponding input capture edge detector senses a defined
transition. The polarity of the active edge is programmable. The level transition which triggers the counter
transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TBSC0 through TBSC1
control registers with x referring to the active channel number). When an active edge occurs on the pin of
an input capture channel, the TIMB latches the contents of the TIMB counter into the TIMB channel
registers, TBCHxH–TBCHxL. Input captures can generate TIMB CPU interrupt requests. Software can
determine that an input capture event has occurred by enabling input capture interrupts or by polling the
status flag bit.
The free-running counter contents are transferred to the TIMB channel status and control register
(TBCHxH–TBCHxL, see 18.8.5 TIMB Channel Registers) on each proper signal transition regardless of
whether the TIMB channel flag (CH0F–CH1F in TBSC0–TBSC1 registers) is set or clear. When the status
flag is set, a CPU interrupt is generated if enabled. The value of the count latched or “captured” is the time
of the event. Because this value is stored in the input capture register 2 bus cycles after the actual event
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
211