MC68HC908EY16 Datasheet, PDF (100/278 Pages) Motorola, Inc – Microcontrollers

Internal Clock Generator (ICG) Module
8.7.6 ICG DCO Stage Register
Address: $003A
Read:
Write:
Bit 7
DSTG7
R
6
DSTG6
R
5
DSTG5
R
4
DSTG4
R
3
DSTG3
R
2
DSTG2
R
1
DSTG1
R
Reset:
R
= Reserved
Unaffected by reset
Figure 8-16. ICG DCO Stage Control Register (ICGDSR)
Bit 0
DSTG0
R
DSTG7:DSTG0 — ICG DCO Stage Control Bits
These bits indicate the number of stages (above the minimum) in the digitally controlled oscillator. The
total number of stages is approximately equal to $1FF, so changing DSTG from $00 to $FF will
approximately double the period. Incrementing DSTG will increase the period (decrease the
frequency) by 0.202 percent to 0.368 percent (decrementing has the opposite effect). DSTG cannot
be written when ICGON is set to prevent inadvertent frequency shifting. When ICGON is set, DSTG is
controlled by the digital loop filter. Since the DCO is active during reset, reset has no effect on DSTG
and the value may vary.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
100
Freescale Semiconductor