MC68HC908EY16 Datasheet, PDF (158/278 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
14.3.2 Active Resets from Internal Sources
An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, POR, or
MENRST as shown in Figure 14-4.
NOTE
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM asserts IRST. The internal reset signal then follows
with the 64-cycle phase as shown in Figure 14-5.
The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RESET
ILLEGAL OPCODE RESET
COP RESET
LVI
INTERNAL RESET
POR
MENRST
Figure 14-4. Sources of Internal Reset
Reset Type
POR/LVI
All Others
Table 14-2. Reset Recovery Timing
Actual Number of Cycles
4163 (4096 + 64 + 3)
67 (64 + 3)
RST
CGMXCLK
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
IAB
VECTOR HIGH
Figure 14-5. Internal Reset Timing
14.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset (POR) module generates a pulse to indicate
that power-on has occurred. The MCU is held in reset while the SIM counter counts out 4096 CGMXCLK
cycles. Another 64 CGMXCLK cycles later, the CPU and memories are released from reset to allow the
reset vector sequence to occur.
At power-on, these events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables CGMOUT.
• Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the internal clock generator.
• The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are
cleared.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
158
Freescale Semiconductor