MC68HC908EY16 Datasheet, PDF (147/278 Pages) Motorola, Inc – Microcontrollers

I/O Registers
slave node must be within ±15% of the master node's oscillator. Since a slave node cannot know if it
is running faster or slower than the master node (prior to synchronization), the LINR bit allows the slave
node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits. The
break symbol length must be verified in software in any case, but the LINR bit serves as a filter,
preventing false detections of break characters that are really 0x00 data characters.
SCP1 and SCP0 — ESCI Baud Rate Register Prescaler Bits
These read/write bits select the baud rate register prescaler divisor as shown in Table 13-7. Reset
clears SCP1 and SCP0.
Table 13-7. ESCI Baud Rate Prescaling
SCP[1:0]
00
01
10
11
Baud Rate Register
Prescaler Divisor (BPD)
1
3
4
13
SCR2–SCR0 — ESCI Baud Rate Select Bits
These read/write bits select the ESCI baud rate divisor as shown in Table 13-8. Reset clears
SCR2–SCR0.
Table 13-8. ESCI Baud Rate Selection
SCR[2:1:0]
000
001
010
011
100
101
110
111
Baud Rate Divisor (BD)
1
2
4
8
16
32
64
128
ESCI Prescaler Register
The ESCI prescaler register (SCPSC) together with the ESCI baud rate register selects the baud rate for
both the receiver and the transmitter.
NOTE
There are two prescalers available to adjust the baud rate. One in the ESCI
baud rate register and one in the ESCI prescaler register.
Address:
Read:
Write:
Reset:
$0017
Bit 7
6
5
4
3
2
1
PDS2
PDS1
PDS0 PSSB4 PSSB3 PSSB2 PSSB1
0
0
0
0
0
0
0
Figure 13-17. ESCI Prescaler Register (SCPSC)
Bit 0
PSSB0
0
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
147