MC68HC908EY16 Datasheet, PDF (176/278 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI) Module
BUS
CLOCK
WRITE
TO SPDR
INITIATION DELAY
MOSI
SCK
CPHA = 1
SCK
CPHA = 0
SCK CYCLE
NUMBER
MSB
BIT 6
BIT 5
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
BUS
CLOCK
WRITE
TO SPDR
BUS
CLOCK
EARLIEST LATEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
LATEST
EARLIEST
SCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
LATEST
Figure 15-6. Transmission Start Delay (Master)
15.6 Error Conditions
Two flags signal SPI error conditions:
1. Overflow (OVRF in SPSCR) — Failing to read the SPI data register before the next byte enters the
shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and
the unread byte still can be read by accessing the SPI data register. OVRF is in the SPI status and
control register.
2. Mode fault error (MODF in SPSCR) — The MODF bit indicates that the voltage on the slave select
pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register.
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
176
Freescale Semiconductor