MC68HC908EY16 Datasheet, PDF (87/278 Pages) Motorola, Inc – Microcontrollers

Functional Description
8.3.5 Clock Selection Circuit
The clock selection circuit, shown in Figure 8-8, contains two clock switches which generate the oscillator
output clock (CGMXCLK) and the timebase clock (TBMCLK) from either the internal clock (ICLK) or the
external clock (ECLK). The clock selection circuit also contains a divide-by-two circuit which creates the
clock generator output clock (CGMOUT), which generates the bus clocks.
CS
ICLK
ECLK
IOFF
EOFF
RESET
V_SS
ECGON
SELECT
OUTPUT
ICLK
ECLK
SYNCHRONIZING
DIV2
IOFF
CLOCK
EOFF
SWITCHER
FORCE_I
FORCE_E
SELECT
OUTPUT
ICLK
ECLK
IOFF
EOFF
SYNCHRONIZING
CLOCK
SWITCHER
FORCE_I
FORCE_E
CGMXCLK
CGMOUT
TBMCLK
NAME
CONFIGURATION REGISTER BIT
NAME
REGISTER BIT
NAME
TOP LEVEL SIGNAL
NAME
MODULE SIGNAL
Figure 8-8. Clock Selection Circuit Block Diagram
8.3.5.1 Clock Selection Switches
The first switch creates the oscillator output clock (CGMXCLK) from either the internal clock (ICLK) or the
external clock (ECLK), based on the clock select bit (CS; set selects ECLK, clear selects ICLK). When
switching the CS bit, both ICLK and ECLK must be on (ICGON and ECGON set). The clock being
switched to also must be stable (ICGS or ECGS set).
The second switch creates the timebase clock (TBMCLK) from ICLK or ECLK based on the external clock
on bit. When ECGON is set, the switch automatically selects the external clock, regardless of the state of
the ECGS bit.
8.3.5.2 Clock Switching Circuit
To robustly switch between the internal clock (ICLK) and the external clock (ECLK), the switch assumes
the clocks are completely asynchronous, so a synchronizing circuit is required to make the transition.
When the select input (the clock select bit for the oscillator output clock switch or the external clock on bit
for the timebase clock switch) is changed, the switch will continue to operate off the original clock for
between one and two cycles as the select input is transitioned through one side of the synchronizer. Next,
the output will be held low for between one and two cycles of the new clock as the select input transitions
through the other side. Then the output starts switching at the new clock’s frequency. This transition
guarantees that no glitches will be seen on the output even though the select input may change
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
Freescale Semiconductor
87