PIC18F2331_07 Datasheet, PDF (87/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
DECFSZ
GOTO
BCF
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
COUNTER_HI
PROGRAM_LOOP
EECON1, WREN
; disable interrupts
; required sequence
; write 55H
; write 0AAH
; start program (CPU stall)
; re-enable interrupts
; loop until done
; disable write to memory
6.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and
reprogrammed if needed. The WRERR bit is set when
a write operation is interrupted by a MCLR Reset, or a
WDT Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
6.6 Flash Program Operation During
Code Protection
See Section 22.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Name Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
TBLPTRU —
—
bit 21⁽¹⁾ Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 --00 0000
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 0000 0000
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 0000 0000
TABLAT Program Memory Table Latch
0000 0000 0000 0000
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF 0000 000x 0000 000u
EECON2 EEPROM Control Register 2 (not a physical register)
0000 0000 0000 0000
EECON1 EEPGD CFGS
—
FREE WRERR WREN
WR
RD xx-0 x000 uu-0 u000
IPR2
OSCFIP
—
—
EEIP
—
LVDIP
—
CCP2IP 1--1 -1-1 1--1 -1-1
PIR2
OSCFIF
—
—
EEIF
—
LVDIF
—
CCP2IF 0--0 -0-0 0--0 -0-0
PIE2
OSCFIE
—
—
EEIE
—
LVDIE
—
CCP2IE 0--0 -0-0 0--0 -0-0
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 85