PIC18F2331_07 Datasheet, PDF (163/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
16.1 Input Capture
The Input Capture (IC) submodule implements the
following features:
• Three channels of independent input capture
(16-bits/channel) on the CAP1, CAP2 and CAP3
pins
• Edge-Trigger, Period or Pulse-Width
Measurement Operating modes for each channel
• Programmable prescaler on every input capture
channel
• Special Event Trigger output (IC1 only)
• Selectable noise filters on each capture input
Input Channel 1 (IC1) includes a Special Event
Trigger that can be configured for use in Velocity Mea-
surement mode. Its block diagram is shown in
Figure 16-2. IC2 and IC3 are similar, but lack the
Special Event Trigger features or additional velocity
measurement logic. A representative block diagram is
shown in Figure 16-3. Please note that the time base
is Timer5.
FIGURE 16-2:
INPUT CAPTURE BLOCK DIAGRAM FOR IC1
CAP1 Pin
Noise
Filter
Prescaler
1, 4, 16
and
Mode
Select
3
FLTCK<2:0>
4
CAP1M<3:0> Q Clocks
IC1IF
IC1_TR
1
MUX
0
velcap⁽²⁾ VELM
Clock/
Reset/
Interrupt
Decode
Logic
Special
Event Trigger
Reset
CAP1BUF_clk
First Event
Reset
Q Clocks CAP1M<3:0>
CAP1BUF/VELR⁽¹⁾
Clock
TMR5
Timer5 Logic
Reset
Reset
Control
Timer
Reset
Control
Timer5 Reset
Note 1: CAP1BUF register is reconfigured as VELR register when QEI mode is active.
2: QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 161