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PIC18F2331_07 Datasheet, PDF (325/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D | |||
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PIC18F2331/2431/4331/4431
RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Right f (No Carry)
[ label ] RRNCF f [,d [,a]]
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
(f<n>) â dest<n â 1>,
(f<0>) â dest<7>
N, Z
0100 00da ffff ffff
The contents of register âfâ are rotated
one bit to the right. If âdâ is â0â, the result
is placed in W. If âdâ is â1â, the result is
placed back in register âfâ (default). If âaâ
is â0â, the Access Bank will be selected,
overriding the BSR value. If âaâ is â1â,
then the bank will be selected as per
the BSR value (default).
register f
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
1
1
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example 1:
RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2:
RRNCF REG, W
Before Instruction
W
=?
REG = 1101 0111
After Instruction
W
=
REG =
1110 1011
1101 0111
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Set f
[ label ] SETF f [,a]
0 ⤠f ⤠255
a â [0,1]
FFh â f
None
0110 100a ffff ffff
The contents of the specified register
are set to FFh. If âaâ is â0â, the Access
Bank will be selected, overriding the
BSR value. If âaâ is â1â, then the bank will
be selected as per the BSR value
(default).
1
1
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write
register âfâ
Example:
SETF
Before Instruction
REG
=
After Instruction
REG
=
REG
0x5A
0xFF
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 323
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