PIC18F2331_07 Datasheet, PDF (180/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 16-14:
NOISE FILTER TIMING DIAGRAM (CLOCK DIVIDER = 1:1)
TQEI = 16 TCY
TCY
CAP1/INDX Pin⁽¹⁾
(input to filter)
Noise Glitch⁽³⁾
Noise Glitch⁽³⁾
CAP1/INDX Input⁽²⁾
(output from filter) _{TGD = 3TCY}
Note 1: Only CAP1/INDX pin input is shown for simplicity. Similar event timing occurs on CAP2/QEA and CAP3/QEB pins.
2: Noise filtering occurs in shaded portions of CAP1 input.
3: Filter’s group delay: TGD = 3 TCY.
16.4 IC and QEI Shared Interrupts
The IC and QEI submodules can each generate three
distinct interrupt signals; however, they share the use
of the same three interrupt flags in register PIR3. The
meaning of a particular interrupt flag at any given time
depends on which module is active at the time the
interrupt is set. The meaning of the flags in context are
summarized in Table 16-7.
When the IC submodule is active, the three flags (IC1IF,
IC2QEIF and IC3DRIF) function as interrupt-on-capture
event flags for their respective input capture channels.
The channel must be configured for one of the events
that will generate an interrupt (see Section 16.1.7 “IC
Interrupts” for more information).
When the QEI is enabled, the IC1IF interrupt flag
indicates an interrupt caused by a velocity
measurement event, usually an update of the VELR
register. The IC2QEIF interrupt indicates that a position
measurement event has occurred. IC3DRIF indicates
that a direction change has been detected.
TABLE 16-7: MEANING OF IC AND QEI
INTERRUPT FLAGS
Interrupt
Flag
IC Mode
Meaning
QEI Mode
IC1IF IC1 Capture Event Velocity Register Update
IC2QEIF IC2 Capture Event Position Measurement
Update
IC3DRIF IC3 Capture Event Direction Change
16.5 Operation in Sleep Mode
16.5.1 3x INPUT CAPTURE IN SLEEP
MODE
Since the input capture can operate only when its time
base is configured in a Synchronous mode, the input
capture will not capture any events. This is because the
device’s internal clock has been stopped and any inter-
nal timers in Synchronous modes will not increment.
The prescaler will continue to count the events (not
synchronized).
When the specified capture event occurs, the CAPx
interrupt will be set. The Capture Buffer register will be
updated upon wake-up from sleep to the current TMR5
value. If the CAPx interrupt is enabled, the device will
wake-up from Sleep. This effectively enables all input
capture channels to be used as the external interrupts.
16.5.2 QEI IN SLEEP MODE
All QEI functions are halted in Sleep mode.
DS39616C-page 178
Preliminary
© 2007 Microchip Technology Inc.