PIC18F2331_07 Datasheet, PDF (35/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
3.0 POWER-MANAGED MODES
The PIC18F2331/2431/4331/4431 devices offer a total
of six operating modes for more efficient power
management (see Table 3-1). These operating modes
provide a variety of options for selective power
conservation in applications where resources may be
limited (i.e., battery-powered devices).
There are three categories of power-managed modes:
• Sleep mode
• Idle modes
• Run modes
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.
The clock switching feature offered in other PIC18
devices (i.e., using the Timer1 oscillator in place of the
primary oscillator), and the Sleep mode offered by all
PIC^® devices (where all system clocks are stopped), are
both offered in the PIC18F2331/2431/4331/4431
devices (SEC_RUN and Sleep modes, respectively).
However, additional power-managed modes are
available that allow the user greater flexibility in deter-
mining what portions of the device are operating. The
power-managed modes are event driven; that is, some
specific event must occur for the device to enter or (more
particularly) exit these operating modes.
For PIC18F2331/2431/4331/4431 devices, the power-
managed modes are invoked by using the existing
SLEEP instruction. All modes exit to PRI_RUN mode
when triggered by an interrupt, a Reset or a WDT time-
out (PRI_RUN mode is the normal full power execution
mode; the CPU and peripherals are clocked by the
primary oscillator source). In addition, power-managed
Run modes may also exit to Sleep mode or their
corresponding Idle mode.
3.1 Selecting Power-Managed Modes
Selecting a power-managed mode requires deciding if
the CPU is to be clocked or not, and selecting a clock
source. The IDLEN bit controls CPU clocking, while the
SCS1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.
3.1.1 CLOCK SOURCES
The clock source is selected by setting the SCS bits of
the OSCCON register. Three clock sources are avail-
able for use in power-managed Idle modes: the primary
clock (as configured in Configuration Register 1H), the
secondary clock (Timer1 oscillator) and the internal
oscillator block. The secondary and internal oscillator
block sources are available for the power-managed
modes (PRI_RUN mode is the normal full power
execution mode; the CPU and peripherals are clocked
by the primary oscillator source).
TABLE 3-1: POWER-MANAGED MODES
Mode
OSCCON<7,1:0>
IDLEN SCS1:SCS0
Module Clocking
CPU Peripherals
Available Clock and Oscillator Source
Sleep
0
PRI_RUN
0
00
Off
Off
None – All clocks are disabled
00
Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC⁽¹⁾
This is the normal full power execution mode.
SEC_RUN
0
RC_RUN
0
01
Clocked Clocked Secondary – Timer1 Oscillator
1x
Clocked Clocked Internal Oscillator Block⁽¹⁾
PRI_IDLE
1
00
Off
Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE
1
01
Off
Clocked Secondary – Timer1 Oscillator
RC_IDLE
1
1x
Off
Clocked Internal Oscillator Block⁽¹⁾
Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 33