PIC18F2331_07 Datasheet, PDF (75/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
5.12 Indirect Addressing, INDF and
FSR Registers
Indirect Addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 5-8
shows how the fetched instruction is modified prior to
being executed.
Indirect Addressing is possible by using one of the
INDFn registers. Any instruction using the INDFn reg-
ister actually accesses the register pointed to by the
File Select Register, FSRn. Reading the INDFn register
itself, indirectly (FSRn = 0), will read 00h. Writing to the
INDFn register, indirectly, results in a no operation. The
FSRn register contains a 12-bit address, which is
shown in Figure 5-9.
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is Indirect Addressing.
Example 5-5 shows a simple use of Indirect Address-
ing to clear the RAM in Bank 1 (locations 100h-1FFh)
in a minimum number of instructions.
EXAMPLE 5-5:
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
NEXT
LFSR
CLRF
BTFSS
GOTO
CONTINUE
FSR0, 0x100
POSTINC0
FSR0H, 1
NEXT
;
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
; NO, clear next
; YES, continue
There are three Indirect Addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12 bits wide. To store the 12 bits of
addressing information, two 8-bit registers are
required:
1. FSR0: composed of FSR0H:FSR0L.
2. FSR1: composed of FSR1H:FSR1L.
3. FSR2: composed of FSR2H:FSR2L.
In addition, there are registers, INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates Indirect Address-
ing, with the value in the corresponding FSR register
being the address of the data. If an instruction writes a
value to INDF0, the value will be written to the address
pointed to by FSR0H:FSR0L. A read from INDF1 reads
the data from the address pointed to by
FSR1H:FSR1L. INDFn can be used in code anywhere
an operand can be used.
If INDF0, INDF1 or INDF2 are read indirectly via a
FSRn, all ‘0’s are read (Zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOP instruction and the
Status bits are not affected.
5.12.1 INDIRECT ADDRESSING
OPERATION
Each FSRn register has an INDFn register associated
with it, plus four additional register addresses. Perform-
ing an operation using one of these five registers
determines how the FSRn will be modified during
Indirect Addressing.
When data access is performed using one of the five
INDFn locations, the address selected will configure
the FSRn register to:
• Do nothing to FSRn after an indirect access (no
change) – INDFn
• Auto-decrement FSRn after an indirect access
(post-decrement) – POSTDECn
• Auto-increment FSRn after an indirect access
(post-increment) – POSTINCn
• Auto-increment FSRn before an indirect access
(pre-increment) – PREINCn
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) – PLUSWn
When using the auto-increment or auto-decrement
features, the effect on the FSRn is not reflected in the
STATUS register. For example, if Indirect Addressing
causes the FSRn to equal ‘0’, the Z bit will not be set.
Auto-incrementing or auto-decrementing a FSRn
affects all 12 bits. That is, when FSRnL overflows from
an increment, FSRnH will be incremented
automatically.
Adding these features allows the FSRn to be used as a
Stack Pointer in addition to its uses for table operations
in data memory.
Each FSRn has an address associated with it that
performs an indexed indirect access. When a data
access to this INDFn location (PLUSWn) occurs, the
FSRn is configured to add the signed value in the
WREG register and the value in FSRn to form the
address before an indirect access. The FSRn value is
not changed. The WREG offset range is -128 to +127.
If an FSRn register contains a value that points to one
of the INDFn, an indirect read will read 00h (Zero bit is
set), while an indirect write will be equivalent to a NOP
(Status bits are not affected).
If an Indirect Addressing write is performed when the
target address is an FSRnH or FSRnL register, the
data is written to the FSRn register, but no pre- or
post-increment/decrement is performed.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 73