PIC18F2331_07 Datasheet, PDF (356/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
25.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 25-5:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
CLKO
1
3
3
4
4
2
TABLE 25-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
1A
FOSC
External CLKI Frequency⁽¹⁾
DC
Oscillator Frequency⁽¹⁾
DC
40
MHz EC, ECIO
4
MHz RC osc
0.1
4
MHz XT osc
4
25
MHz HS osc
4
10
MHz HS + PLL osc
5
200
kHz LP Osc mode
1
TOSC
External CLKI Period⁽¹⁾
25
—
ns EC, ECIO
Oscillator Period⁽¹⁾
250
—
ns RC osc
250
10,000 ns XT osc
25
250
ns HS osc
100
250
ns HS + PLL osc
25
—
μs LP osc
2
TCY
Instruction Cycle Time⁽¹⁾
100
—
ns TCY = 4/FOSC
3
TosL,
External Clock in (OSC1)
30
—
ns XT osc
TosH
High or Low Time
2.5
—
μs LP osc
10
—
ns HS osc
4
TosR, External Clock in (OSC1)
—
TosF
Rise or Fall Time
—
20
ns XT osc
50
ns LP osc
—
7.5
ns HS osc
Note 1:
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
DS39616C-page 354
Preliminary
© 2007 Microchip Technology Inc.