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| PIC18F2331_07 Datasheet, PDF (55/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D | |||
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PIC18F2331/2431/4331/4431
TABLE 4-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
IPR2
2331 2431 4331 4431 1--1 -1-1
1--1 -1-1
u--u -u-u
PIR2
2331 2431 4331 4431 0--0 -0-0
0--0 -0-0
u--u -u-u
PIE2
2331 2431 4331 4431 0--0 -0-0
0--0 -0-0
u--u -u-u
IPR1
PIR1
2331 2431 4331 4431
2331 2431 4331 4431
2331 2431 4331 4431
-111 1111
-000 0000
-000 0000
-111 1111
-000 0000
-000 0000
-uuu uuuu
-uuu uuuu(1)
-uuu uuuu(1)
PIE1
2331 2431 4331 4431 0000 0000
0000 0000
uuuu uuuu
2331 2431 4331 4431 -000 0000
-000 0000
-uuu uuuu
OSCTUNE 2331 2431 4331 4431
TRISE(6)
2331 2431 4331 4431
--00 0000
---- -111
--00 0000
---- -111
--uu uuuu
---- -uuu
TRISD
2331 2431 4331 4431 1111 1111
1111 1111
uuuu uuuu
TRISC
2331 2431 4331 4431 1111 1111
1111 1111
uuuu uuuu
TRISB
TRISA(5)
2331 2431 4331 4431
2331 2431 4331 4431
1111 1111
1111 1111(5)
1111 1111
1111 1111(5)
uuuu uuuu
uuuu uuuu(5)
PR5H
2331 2431 4331 4431 1111 1111
1111 1111
uuuu uuuu
PR5L
LATE(6)
2331 2431 4331 4431
2331 2431 4331 4431
1111 1111
---- -xxx
1111 1111
---- -uuu
uuuu uuuu
---- -uuu
LATD
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
LATA(5)
2331 2431 4331 4431
2331 2431 4331 4431
xxxx xxxx
xxxx xxxx(5)
uuuu uuuu
uuuu uuuu(5)
uuuu uuuu
uuuu uuuu(5)
TMR5H
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR5L
PORTE(6)
2331 2431 4331 4431
2331 2431 4331 4431
xxxx xxxx
---- xxxx
uuuu uuuu
---- xxxx
uuuu uuuu
---- uuuu
PORTD
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
2331 2431 4331 4431 xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
PORTA(5)
2331 2431 4331 4431
2331 2431 4331 4431
xxxx xxxx
xx0x 0000(5)
uuuu uuuu
uu0u 0000(5)
uuuu uuuu
uuuu uuuu(5)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as â0â, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read â0â.
6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE
pin, they are disabled and read as â0â. The 28-pin devices have only RE3 on PORTE when MCLR is
disabled.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 53
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