PIC18F2331_07 Datasheet, PDF (69/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
5.9.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 5-1 and Table 5-2.
The SFRs can be classified into two sets; those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFRs are typically distributed among the
peripherals whose functions they control.
The unused SFR locations will be unimplemented and
read as ‘0’s.
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2331/2431/4331/4431 DEVICES
Address Name Address Name Address Name Address Name Address
Name
FFFh TOSU
FFEh TOSH
FFDh TOSL
FFCh STKPTR
FFBh PCLATU
FFAh PCLATH
FF9h PCL
FF8h TBLPTRU
FF7h TBLPTRH
FF6h TBLPTRL
FF5h TABLAT
FF4h PRODH
FF3h PRODL
FF2h INTCON
FF1h INTCON2
FF0h INTCON3
FEFh INDF0
FEEh POSTINC0
FEDh POSTDEC0
FECh PREINC0
FEBh PLUSW0
FEAh FSR0H
FE9h FSR0L
FE8h WREG
FE7h INDF1
FE6h POSTINC1
FE5h POSTDEC1
FE4h PREINC1
FE3h PLUSW1
FE2h FSR1H
FE1h FSR1L
FE0h BSR
FDFh INDF2
FDEh POSTINC2
FDDh POSTDEC2
FDCh PREINC2
FDBh PLUSW2
FDAh FSR2H
FD9h FSR2L
FD8h STATUS
FD7h TMR0H
FD6h TMR0L
FD5h T0CON
FD4h
—
FD3h OSCCON
FD2h LVDCON
FD1h WDTCON
FD0h RCON
FCFh TMR1H
FCEh TMR1L
FCDh T1CON
FCCh TMR2
FCBh
PR2
FCAh T2CON
FC9h SSPBUF
FC8h SSPADD
FC7h SSPSTAT
FC6h SSPCON
FC5h
—
FC4h ADRESH
FC3h ADRESL
FC2h ADCON0
FC1h ADCON1
FC0h ADCON2
FBFh
FBEh
FBDh
FBCh
FBBh
FBAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
ANSEL1
ANSEL0
T5CON
QEICON
—
—
—
—
—
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
BAUDCTL
EEADR
EEDATA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
IPR1
PIR1
PIE1
—
OSCTUNE
ADCON3
ADCHS
—
—
TRISE
TRISD
TRISC
TRISB
TRISA
PR5H
PR5L
—
—
LATE
LATD
LATC
LATB
LATA
TMR5H
TMR5L
—
—
PORTE
PORTD
PORTC
PORTB
PORTA
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
PTCON0
PTCON1
PTMRL
PTMRH
PTPERL
PTPERH
PDC0L
PDC0H
PDC1L
PDC1H
PDC2L
PDC2H
PDC3L
PDC3H
SEVTCMPL
SEVTCMPH
PWMCON0
PWMCON1
DTCON
FLTCONFIG
OVDCOND
OVDCONS
CAP1BUFH
CAP1BUFL
CAP2BUFH
CAP2BUFL
CAP3BUFH
CAP3BUFL
CAP1CON
CAP2CON
CAP3CON
DFLTCON
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 67