PIC18F2331_07 Datasheet, PDF (394/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
Timer5 ............................................................................... 147
Associated Registers ................................................ 151
Interrupt..................................................................... 150
Noise Filter ................................................................ 150
Operation .................................................................. 148
Continuous Count and Single-Shot................... 149
Sleep Mode....................................................... 150
Prescaler ................................................................... 149
Special Event Trigger Output .................................... 150
Special Event Trigger Reset Input ............................ 150
16-Bit Read/Write and Write Modes ......................... 149
16-Bit Read-Modify-Write.......................................... 149
Timing Diagrams
Asynchronous Reception .......................................... 236
Asynchronous Transmission ..................................... 233
Asynchronous Transmission
(Back to Back)................................................... 233
Automatic Baud Rate Calculation ............................. 231
Auto-Wake-up Bit (WUE) During
Normal Operation.............................................. 237
Auto-Wake-up Bit (WUE) During Sleep .................... 237
Brown-out Reset (BOR) ............................................ 357
Capture/Compare/PWM (All CCP Modules) ............. 359
CAPx Interrupts and IC1
Special Event Trigger........................................ 167
CLKO and I/O ........................................................... 356
Clock, Instruction Cycle .............................................. 63
Dead-Time Insertion for
Complementary PWM....................................... 199
Duty Cycle Update Times in Continuous
Up/Down Count Mode....................................... 196
Duty Cycle Update Times in Continuous Up/Down
Count Mode with Double Updates .................... 197
Edge Capture Mode .................................................. 164
Edge-Aligned PWM................................................... 196
EUSART Synchronous Receive
(Master/Slave)................................................... 368
EUSART SynchronousTransmission
(Master/Slave)................................................... 368
Example SPI Master Mode (CKE = 0) ...................... 360
Example SPI Master Mode (CKE = 1) ...................... 361
Example SPI Slave Mode (CKE = 0) ........................ 362
Example SPI Slave Mode (CKE = 1) ........................ 363
External Clock (All Modes Except PLL) .................... 354
Fail-Safe Clock Monitor............................................. 284
Input Capture on State Change ................................ 166
I²C Bus Data ............................................................. 364
I²C Bus Start/Stop Bits.............................................. 364
I²C Reception (7-bit Address) ................................... 221
I²C Transmission (7-bit Address) .............................. 221
Low-Voltage Detect................................................... 266
Low-Voltage Detect Characteristics .......................... 349
Noise Filter ................................................................ 178
Pulse-Width Measurement Mode.............................. 165
PWM Output ............................................................. 157
PWM Output Override (Example 1) .......................... 205
PWM Output Override (Example 2) .......................... 205
PWM Override Bits in Complementary Mode ........... 203
PWM Period Buffer Updates in Continuous
Up/Down Count Mode....................................... 194
PWM Period Buffer Updates in
Free-Running Mode .......................................... 194
PWM Time Base Interrupt, Continuous
Up/Down Count Mode....................................... 191
PWM Time Base Interrupt, Continuous
Up/Down Count Mode with Double Updates .... 192
PWM Time Base Interrupt,
Free-Running Mode.......................................... 189
PWM Time Base Interrupt, Single-Shot Mode.......... 190
QEI Inputs When Sampled by Filter ......................... 173
QEI Reset on Period Match ...................................... 173
QEI Reset with the Index Input ................................. 174
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST), Power-up Timer (PWRT) ............ 357
Send Break Character Sequence ............................. 238
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................. 57
SPI Mode (Master Mode).......................................... 217
SPI Mode (Slave Mode with CKE = 0)...................... 217
SPI Mode (Slave Mode with CKE = 1)...................... 218
SSP I²C Bus Data .................................................... 366
SSP I²C Bus Start/Stop Bits ..................................... 366
Start of Center-Aligned PWM ................................... 197
Synchronous Reception
(Master Mode, SREN) ...................................... 241
Synchronous Transmission ...................................... 239
Synchronous Transmission (Through TXEN) ........... 240
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) ........................................... 57
Time-out Sequence on Power-up
(MCLR Not Tied to VDD): Case 1 ....................... 56
Time-out Sequence on Power-up
(MCLR Not Tied to VDD): Case 2 ....................... 56
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise TPWRT) ............... 56
Timer0 and Timer1 External Clock ........................... 358
Transition for Entry to SEC_IDLE Mode ..................... 38
Transition for Entry to SEC_RUN Mode ..................... 40
Transition for Entry to Sleep Mode ............................. 36
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ......................................... 282
Transition for Wake From PRI_IDLE Mode ................ 37
Transition for Wake From RC_RUN Mode
(RC_RUN to PRI_RUN) ..................................... 39
Transition for Wake From SEC_RUN
Mode (HSPLL).................................................... 38
Transition for Wake From Sleep (HSPLL) .................. 36
Transition to PRI_IDLE Mode ..................................... 37
Transition to RC_IDLE Mode...................................... 39
Transition to RC_RUN Mode ...................................... 41
Velocity Measurement .............................................. 176
Timing Diagrams and Specifications ................................ 354
Capture/Compare/PWM Requirements
(All CCP Modules) ............................................ 359
CLKO and I/O Requirements.................................... 356
EUSART Synchronous Receive
Requirements ................................................... 368
EUSART Synchronous Transmission
Requirements ................................................... 368
Example SPI Mode Requirements
(Master Mode, CKE = 0)................................... 360
Example SPI Mode Requirements
(Master Mode, CKE = 1)................................... 361
Example SPI Mode Requirements
(Slave Mode, CKE = 0)..................................... 362
Example SPI Slave Mode Requirements
(CKE = 1).......................................................... 363
External Clock Requirements ................................... 354
DS39616C-page 392
Preliminary
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