PIC18F2331_07 Datasheet, PDF(213/400 Page) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

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PIC18F2331_07 Datasheet, PDF (213/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

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PIC18F2331/2431/4331/4431

TABLE 17-6: REGISTERS ASSOCIATED WITH THE POWER CONTROL PWM MODULE

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

Resets

INTCON

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u

IPR3

â

â

â

PTIP IC3DRIP IC2QEIP IC1IP TMR5IP ---1 1111 ---1 1111

PIE3

â

â

â

PTIE IC3DRIE IC2QEIE IC1IE TMR5IE ---0 0000 ---0 0000

PIR3

â

â

â

PTIF IC3DRIF IC2QEIF IC1IF TMR5IF ---0 0000 ---0 0000

PTCON0

PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 0000 0000 0000 0000

PTCON1

PTEN PTDIR

â

â

â

â

â

â 00-- ----

PTMRL(1)

PWM Time Base Register (lower 8 bits)

0000 0000

PTMRH(1)

UNUSED

PWM Time Base Register (upper 4 bits)

---- 0000

PTPERL(1) PWM Time Base Period Register (lower 8 bits)

1111 1111

PTPERH(1)

UNUSED

PWM Time Base Period Register (upper 4 bits) ---- 1111

SEVTCMPL(1) PWM Special Event Compare Register (lower 8 bits)

0000 0000

SEVTCMPH(1)

UNUSED

PWM Special Event Compare Register

(upper 4 bits)

---- 0000

PWMCON0

â

PWMEN2 PWMEN1 PWMEN0 PMOD3(2) PMOD2 PMOD1 PMOD0 -111 0000

00-- ----

0000 0000

---- 0000

1111 1111

---- 1111

0000 0000

---- 0000

-111 0000

PWMCON1 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR

â

UDIS OSYNC 0000 0-00 0000 0-00

DTCON

FLTCONFIG

OVDCOND

OVDCONS

PDC0L(1)

PDC0H(1)

PDC1L(1)

PDC1H(1)

PDC2L(1)

PDC2H(1)

PDC3L(1,2)

PDC3H(1,2)

DTPS1

BRFEN

POVD7(2)

POUT7(2)

DTPS0

FLTBS(2)

POVD6(2)

POUT6(2)

DT5

DT4

FLTBMOD(2) FLTBEN(2)

POVD5 POVD4

POUT5 POUT4

DT3

FLTCON

POVD3

POUT3

DT2

FLTAS

POVD2

POUT2

PWM Duty Cycle #0L Register (lower 8 bits)

UNUSED

PWM Duty Cycle #0H Register (upper 6 bits)

PWM Duty Cycle #1L register (lower 8 bits)

UNUSED

PWM Duty Cycle #1H Register (upper 6 bits)

PWM Duty Cycle #2L Register (lower 8 bits)

UNUSED

PWM Duty Cycle #2H Register (upper 6 bits)

PWM Duty Cycle #3L Register (lower 8 bits)

UNUSED

PWM Duty Cycle #3H Register (upper 6 bits)

DT1

DT0 0000 0000 0000 0000

FLTAMOD FLTAEN 0000 0000 0000 0000

POVD1 POVD0 1111 1111 1111 1111

POUT1 POUT0 0000 0000 0000 0000

0000 0000 0000 0000

--00 0000 --00 0000

0000 0000 0000 0000

--00 0000 --00 0000

0000 0000 0000 0000

--00 0000 --00 0000

0000 0000 0000 0000

--00 0000 --00 0000

Legend:

Note 1:

2:

- = Unimplemented, read as â0â, u = unchanged. Shaded cells are not used with the Power Control PWM.

Double-buffered register pairs. Refer to text for explanation of how these registers are read and written to.

Unimplemented in PIC18F2331/2431 devices; maintain these bits clear. Reset values shown are for PIC18F4331/4431 devices.

Â© 2007 Microchip Technology Inc.

Preliminary

DS39616C-page 211

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