PIC18F2331_07 Datasheet, PDF (49/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
4.0 RESET
The PIC18F2331/2431/4331/4431 devices differentiate
between various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-2.
These bits are used in software to determine the nature
of the Reset. See Table 4-3 for a full description of the
Reset states of all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
The enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
The MCLR input provided by the MCLR pin can be dis-
abled with the MCLRE bit in Configuration Register 3H
(CONFIG3H<7>). See Section 22.1 “Configuration
Bits” for more information.
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
MCLR
External Reset
MCLRE
( )_IDLE
Sleep
WDT
Time-out
VDD Rise POR Pulse
Detect
VDD
Brown-out
Reset
BOREN
S
OSC1
OST/PWRT
OST ^{1024 Cycles}
10-Bit Ripple Counter
Chip_Reset
R
Q
32 μs
INTRC⁽¹⁾
PWRT 65.5 ms
11-Bit Ripple Counter
Enable PWRT
Enable OST⁽²⁾
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-1 for time-out situations.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 47