PIC18F2331_07 Datasheet, PDF (81/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
REGISTER 6-1: EECON1: FLASH PROGRAM/DATA EEPROM CONTROL REGISTER 1
R/W-x
R/W-x
U-0
R/W-0
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
CFGS
—
FREE
WRERR⁽¹⁾
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
S = Settable only bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access program Flash memory
0 = Access data EEPROM memory
bit 6
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access program Flash or data EEPROM memory
bit 5
Unimplemented: Read as ‘0’
bit 4
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by
completion of erase operation – TBLPTR<5:0> are ignored)
0 = Perform write only
bit 3
WRERR: EEPROM Error Flag bit⁽¹⁾
1 = A write operation is prematurely terminated (any Reset during self-timed programming)
0 = The write operation completed normally
bit 2
WREN: Write Enable bit
1 = Allows erase or write cycles
0 = Inhibits erase or write cycles
bit 1
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.)
0 = Write cycle completed
bit 0
RD: Read Control bit
1 = Initiates a memory read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in soft-
ware. RD bit cannot be set when EEPGD = 1.)
0 = Read completed
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 79