PIC18F2331_07 Datasheet, PDF (365/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 25-14:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
bit 6 - - - - - -1
LSb
75, 76
77
SDI
MSb In
bit 6 - - - -1
LSb In
74
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
TCY
—
71
TscH
71A
SCK Input High Time
(Slave mode)
Continuous
Single byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single byte
1.25 TCY + 30 —
40
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
100
—
75
TdoR
SDO Data Output Rise Time
PIC18FXX31
—
25
PIC18LFXX31
45
76
TdoF
SDO Data Output Fall Time
—
25
77
TssH2doZ SS ↑ to SDO Output High-Impedance
10
50
78
TscR
SCK Output Rise Time
(Master mode)
PIC18FXX31
PIC18LFXX31
—
25
—
45
79
TscF
SCK Output Fall Time (Master mode)
—
25
80
TscH2doV, SDO Data Output Valid after SCK PIC18FXX31
TscL2doV Edge
PIC18LFXX31
—
50
—
100
82
TssL2doV SDO Data Output Valid after SS ↓ PIC18FXX31
Edge
PIC18LFXX31
—
50
—
100
83
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter 73A.
2: Only if Parameter 71A and 72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 363