PIC18F2331_07 Datasheet, PDF (200/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
17.6.5 COMPLEMENTARY PWM
OPERATION
The Complementary mode of PWM operation is useful
to drive one or more power switches in half-bridge
configuration as shown in Figure 17-16. This inverter
topology is typical for a 3-phase induction motor,
brushless DC motor or a 3-phase Uninterruptible
Power Supply (UPS) control applications.
Each upper/lower power switch pair is fed by a
complementary PWM signal. Dead time may be
optionally inserted during device switching, where both
outputs are inactive for a short period (see
Section 17.7 “Dead-Time Generators”).
In Complementary mode, the duty cycle comparison
units are assigned to the PWM outputs as follows:
• PDC0 register controls PWM1/PWM0 outputs
• PDC1 register controls PWM3/PWM2 outputs
• PDC2 register controls PWM5/PWM4 outputs
• PDC3 register controls PWM7/PWM6 outputs
PWM1/3/5/7 are the main PWMs that are controlled by
the PDCx registers and PWM0/2/4/6 are the
complemented outputs. When using the PWMs to
control the half bridge, the odd numbered PWMs can
be used to control the upper power switch and the even
numbered PWMs used for the lower switches.
FIGURE 17-16:
TYPICAL LOAD FOR
COMPLEMENTARY PWM
OUTPUTS
+V
3-Phase
Load
The Complementary mode is selected for each PWM
I/O pin pair by clearing the appropriate PMODx bit in
the PWMCON0 register. The PWM I/O pins are set to
Complementary mode by default upon all kinds of
device Resets.
DS39616C-page 198
Preliminary
© 2007 Microchip Technology Inc.