PIC18F2331_07 Datasheet, PDF (71/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page:
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0 0000 q000 30, 51
LVDCON
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0 --00 0101 51, 265
WDTCON
WDTW
—
—
—
—
—
—
SWDTEN 0--- ---0 51, 281
RCON
IPEN
—
—
RI
TO
PD
POR
BOR
0--1 11q0 49, 76, 107
TMR1H
Timer1 Register High Byte
xxxx xxxx 51, 143
TMR1L
Timer1 Register Low Byte
xxxx xxxx 51, 143
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 51, 139
TMR2
Timer2 Register
0000 0000 51, 145
PR2
Timer2 Period Register
1111 1111 51, 145
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 51, 145
SSPBUF
SSPADD
SSP Receive Buffer/Transmit Register
SSP Address Register in I²C™ Slave mode. SSP Baud Rate Reload Register in I²C Master mode.
xxxx xxxx
0000 0000
51, 222
51, 222
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 51, 214
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000 51, 215
ADRESH
A/D Result Register High Byte
xxxx xxxx 52, 261
ADRESL
A/D Result Register Low Byte
xxxx xxxx 52, 261
ADCON0
—
—
ACONV
ACSCH ACMOD1 ACMOD0 GO/DONE ADON --00 0000 52, 246
ADCON1
VCFG1
VCFG0
—
FIFOEN BFEMT BFOVFL ADPNT1 ADPNT0 00-0 0000 52, 247
ADCON2
ADFM
ACQT3
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0 0000 0000 52, 248
ADCON3
ADRS1
ADRS0
—
SSRC4
SSRC3
SSRC2
SSRC1
SSRC0 00-0 0000 52. 249
ADCHS
GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 GASEL1 GASEL0 0000 0000 52, 250
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 52, 153
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx 52, 153
CCP1CON
—
—
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 52, 156,
149
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx 52, 153
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 52, 153
CCP2CON
ANSEL1
ANSEL0
T5CON
—
—
ANS7⁽⁵⁾
T5SEN
—
—
ANS6⁽⁵⁾
RESEN⁽⁵⁾
DC2B1
—
ANS5⁽⁵⁾
T5MOD
DC2B0
—
ANS4
T5PS1
CCP2M3
—
ANS3
T5PS0
CCP2M2
—
ANS2
T5SYNC
CCP2M1
—
ANS1
TMR5CS
CCP2M0
ANS8⁽⁵⁾
ANS0
TMR5ON
--00 0000
---- ---1
1111 1111
0000 0000
52, 156
52, 251
52, 251
52, 147
QEICON
VELM
QERR UP/DOWN QEIM2
QEIM1
QEIM0
PDEC1
PDEC0 0000 0000 52, 170
SPBRGH EUSART Baud Rate Generator Register High Byte
0000 0000 52, 227
SPBRG
EUSART Baud Rate Generator Register Low Byte
0000 0000 52, 227
RCREG
EUSART Receive Register
0000 0000 52, 235,
234
TXREG
EUSART Transmit Register
0000 0000 52, 232,
234
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 52, 224
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 52, 225
BAUDCTL
—
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN -1-1 0-00 52, 226
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented.
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
‘0’ in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital inputs and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as
analog inputs and read ‘0’ following a Reset.
These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’.
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 reads ‘0’. This bit is read-only.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 69