PIC18F2331_07 Datasheet, PDF (225/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
19.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is one of the
two serial I/O modules available in the PIC18F2331/
2431/4331/4431 family of microcontrollers. EUSART is
also known as a Serial Communications Interface or
SCI.
The EUSART can be configured as a full-duplex
asynchronous system that can communicate with
peripheral devices, such as CRT terminals and
personal computers. It can also be configured as a half-
duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
The EUSART module implements additional features,
including automatic baud rate detection and
calibration, automatic wake-up on Sync Break
reception and 12-bit Break character transmit. These
features make it ideally suited for use in Local
Interconnect Network (LIN) bus systems.
The EUSART can be configured in the following
modes:
• Asynchronous (full-duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half-duplex) with
selectable clock polarity
• Synchronous – Slave (half-duplex) with selectable
clock polarity
In order to configure pins RC6/TX/CK/SS and RC7/RX/
DT/SDO as the Enhanced Universal Synchronous
Asynchronous Receiver Transmitter:
• SPEN (RCSTA<7>) bit must be set ( = 1),
• TRISC<6> bit must be set ( = 1), and
• TRISC<7> bit must be set ( = 1).
Note:
The EUSART control will automatically
reconfigure the pin from input to output as
needed.
The operation of the Enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCTL)
These are detailed on the following pages in
Register 19-1, Register 19-2 and Register 19-3,
respectively.
19.1 Asynchronous Operation in
Power-Managed Modes
The EUSART may operate in Asynchronous mode
while the peripheral clocks are being provided by the
internal oscillator block. This makes it possible to
remove the crystal or resonator that is commonly con-
nected as the primary clock on the OSC1 and OSC2
pins.
The factory calibrates the internal oscillator block out-
put (INTOSC) for 8 MHz (see Table 25-6). However,
this frequency may drift as VDD or temperature
changes, and this directly affects the asynchronous
baud rate. Two methods may be used to adjust the
baud rate clock, but both require a reference clock
source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output back to 8 MHz.
Adjusting the value in the OSCTUNE register allows for
fine resolution changes to the system clock source (see
Section 3.6 “INTOSC Frequency Drift” for more
information).
The other method adjusts the value in the Baud Rate
Generator (BRG). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 223