PIC18F2331_07 Datasheet, PDF (389/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
Equations
A/D Acquisition Time................................................. 255
Conversion Time for Multi-Channel Modes............... 260
Minimum A/D Holding Capacitor
Charging Time .................................................. 255
PWM Period for Continuous Up/Down
Count Mode ...................................................... 193
PWM Period for Free-Running Mode........................ 193
PWM Resolution ....................................................... 193
16 x 16 Signed Multiplication Algorithm ...................... 92
16 x 16 Unsigned Multiplication Algorithm .................. 92
Errata .................................................................................... 7
EUSART
Asynchronous Mode ................................................. 232
Associated Registers, Receive ......................... 236
Associated Registers, Transmit ........................ 234
Auto-Wake-up on Sync Break .......................... 237
Receiver............................................................ 235
Receiving a Break Character ............................ 238
Setting Up 9-Bit Mode with
Address Detect ......................................... 235
Transmitter........................................................ 232
12-Bit Break Character Sequence .................... 238
Baud Rate Generator (BRG)..................................... 227
Associated Registers ........................................ 228
Auto-Baud Rate Detect ..................................... 231
Baud Rate Error, Calculating ............................ 228
Baud Rates, Asynchronous Modes .................. 228
High Baud Rate Select (BRGH Bit) .................. 227
Power-Managed Mode Operation..................... 227
Sampling ........................................................... 227
Serial Port Enable (SPEN Bit)................................... 223
Synchronous Master Mode ....................................... 239
Associated Registers, Receive ......................... 241
Associated Registers, Transmit ........................ 240
Reception.......................................................... 241
Transmission .................................................... 239
Synchronous Slave Mode ......................................... 242
Associated Registers, Receive ......................... 243
Associated Registers, Transmit ........................ 242
Reception.......................................................... 243
External Clock Input ............................................................ 25
F
Fail-Safe Clock Monitor............................................. 269, 283
Exiting ....................................................................... 283
Interrupts in Power-Managed Modes........................ 284
POR or Wake From Sleep ........................................ 284
WDT During Oscillator Failure .................................. 283
Fail-Safe Clock Monitor (FSCM) ....................................... 269
Fast Register Stack............................................................. 62
Flash Program Memory ...................................................... 77
Associated Registers .................................................. 85
Control Registers ........................................................ 78
Erase Sequence ......................................................... 82
Erasing........................................................................ 82
Operation During Code-Protect .................................. 85
Reading....................................................................... 81
TABLAT Register ........................................................ 80
Table Pointer............................................................... 80
Boundaries Based on Operation......................... 80
Table Pointer Boundaries ........................................... 80
Table Reads and Table Writes ................................... 77
Unexpected Termination of Write
Operation............................................................ 85
Write Sequence .......................................................... 83
Write Verify ................................................................. 85
Writing ........................................................................ 83
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 310
H
Hardware Multiplier............................................................. 91
Introduction................................................................. 91
Operation.................................................................... 91
Performance Comparison........................................... 91
HSPLL ................................................................................ 24
I
I/O Ports ........................................................................... 109
ID Locations.............................................................. 269, 288
INCF ................................................................................. 310
INCFSZ............................................................................. 311
In-Circuit Debugger........................................................... 288
In-Circuit Serial Programming (ICSP)....................... 269, 288
Independent PWM Mode .................................................. 201
Duty Cycle Assignment ............................................ 201
Indirect Addressing
INDF and FSR Registers ............................................ 73
Operation.................................................................... 73
Indirect Addressing Operation ............................................ 74
Indirect File Operand .......................................................... 65
INFSNZ............................................................................. 311
Initialization Conditions for All Registers....................... 50–55
Input Capture .................................................................... 161
Entering and Capture Timing.................................... 167
State Change............................................................ 166
Time Base Reset Summary...................................... 168
Instruction Flow/Pipelining .................................................. 63
Instruction Set
ADDLW..................................................................... 295
ADDWF .................................................................... 295
ADDWFC.................................................................. 296
ANDLW..................................................................... 296
ANDWF .................................................................... 297
BC............................................................................. 297
BCF .......................................................................... 298
BN............................................................................. 298
BNC .......................................................................... 299
BNN .......................................................................... 299
BNOV ....................................................................... 300
BNZ .......................................................................... 300
BOV .......................................................................... 303
BRA .......................................................................... 301
BSF........................................................................... 301
BTFSC...................................................................... 302
BTFSS ...................................................................... 302
BTG .......................................................................... 303
BZ ............................................................................. 304
CALL......................................................................... 304
CLRF ........................................................................ 305
CLRWDT .................................................................. 305
COMF ....................................................................... 306
CPFSEQ ................................................................... 306
CPFSGT ................................................................... 307
CPFSLT.................................................................... 307
DAW ......................................................................... 308
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 387