PIC18F2331_07 Datasheet, PDF (73/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page:
PDC0L
PWM Duty Cycle #0L Register (lower 8 bits)
0000 0000
184
PDC0H
UNUSED
PWM Duty Cycle #0H Register (upper 6 bits)
--00 0000
184
PDC1L
PWM Duty Cycle #1L Register (lower 8 bits)
0000 0000
184
PDC1H
UNUSED
PWM Duty Cycle #1H Register (upper 6 bits)
--00 0000
184
PDC2L
PWM Duty Cycle #2L Register (lower 8 bits)
0000 0000
184
PDC2H
PDC3L⁽⁵⁾
PDC3H⁽⁵⁾
UNUSED
PWM Duty Cycle #2H Register (upper 6 bits)
PWM Duty Cycle #3L Register (lower 8 bits)
UNUSED
PWM Duty Cycle #3H Register (upper 6 bits)
--00 0000
184
0000 0000
184
--00 0000
184
SEVTCMPL PWM Special Event Compare Register (lower 8 bits)
0000 0000
N/A
SEVTCMPH
UNUSED
PWM Special Event Compare Register (upper 4 bits) ---- 0000
N/A
PWMCON0
—
PWMEN2 PWMEN1 PWMEN0 PMOD3 PMOD2 PMOD1 PMOD0 -111 0000 54, 187
PWMCON1 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR
—
UDIS
OSYNC 0000 0-00 54, 188
DTCON
FLTCONFIG
OVDCOND
OVDCONS
DTPS1
BRFEN
POVD7⁽⁵⁾
POUT7⁽⁵⁾
DTPS0
FLTBS⁽⁵⁾
POVD6⁽⁵⁾
POUT6⁽⁵⁾
DT5
DT4
FLTBMOD⁽⁵⁾ FLTBEN⁽⁵⁾
POVD5
POVD4
POUT5
POUT4
DT3
FLTCON
POVD3
POUT3
DT2
FLTAS
POVD2
POUT2
DT1
FLTAMOD
POVD1
POUT1
DT0
FLTAEN
POVD0
POUT0
0000 0000
0000 0000
1111 1111
0000 0000
54, 200
54, 209
54, 204
54, 204
CAP1BUFH/ Capture 1 Register High Byte/Velocity Register High Byte
VELRH
xxxx xxxx
54
CAP1BUFL/ Capture 1 Register Low Byte/Velocity Register Low Byte
VELRL
xxxx xxxx
54
CAP2BUFH/ Capture 2 Register High Byte/QEI Position Counter Register High Byte
POSCNTH
xxxx xxxx
54
CAP2BUFL/ Capture 2 Register Low Byte/QEI Position Counter Register Low Byte
POSCNTL
xxxx xxxx
54
CAP3BUFH/ Capture 3 Register High Byte/QEI Max. Count Limit Register High Byte
MAXCNTH
xxxx xxxx
55
CAP3BUFL/ Capture 3 Register Low Byte/QEI Max. Count Limit Register Low Byte
MAXCNTL
xxxx xxxx
55
CAP1CON
—
CAP1REN
—
—
CAP1M3 CAP1M2 CAP1M1 CAP1M0 -0-- 0000 55, 163
CAP2CON
—
CAP2REN
—
—
CAP2M3 CAP2M2 CAP2M1 CAP2M0 -0-- 0000 55, 163
CAP3CON
—
CAP3REN
—
—
CAP3M3 CAP3M2 CAP3M1 CAP3M0 -0-- 0000 55, 163
DFLTCON
—
FLT4EN FLT3EN FLT2EN FLT1EN FLTCK2 FLTCK1 FLTCK0 -000 0000 55, 177
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented.
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
‘0’ in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital inputs and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as
analog inputs and read ‘0’ following a Reset.
These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’.
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 reads ‘0’. This bit is read-only.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 71