PIC18F2331_07 Datasheet, PDF (150/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 14-1:
T5CKI
TMR5CS
T5PS1:T5PS0
T5SYNC
TMR5ON
Special Event
Trigger Input
from IC1
Timer5 Reset
(external)
Set TMR5IF
Special Event
Trigger Output
TIMER5 BLOCK DIAGRAM (16-BIT READ/WRITE MODE SHOWN)
Noise
Filter
1
FOSC/4
Internal
0
Clock
Prescaler
1, 2, 4, 8
2
1
Synchronize
Detect
0
Sleep Input
Internal Data Bus
Timer5
On/Off
8
8
TMR5H
8
Write TMR5L
Read TMR5L
TMR5
8
1
TMR5L
TMR5
High Byte
Timer5 Reset
0
16
Reset
Logic
Comparator
PR5
16
8
PR5L
PR5H
Special
Event
8
Logic
14.1 Timer5 Operation
Timer5 combines two 8-bit registers to function as a
16-bit timer. The TMR5L register is the actual low byte
of the timer; it can be read and written to directly. The
high byte is contained in an unmapped register; it is
read and written to through TMR5H, which serves as
a buffer. Each register increments from 00h to FFh.
A second register pair, PR5H and PR5L, serves as the
Period register; it sets the maximum count for the
TMR5 register pair. When TMR5 reaches the value of
PR5, the timer rolls over to 00h and sets the TMR5IF
interrupt flag. A simplified block diagram of the Timer5
module is shown in Figure 2-1.
Note:
The Timer5 may be used as a general pur-
pose timer and as the time base resource to
the Motion Feedback Module (Input Capture
or Quadrature Encoder Interface).
Timer5 supports three configurations:
• 16-Bit Synchronous Timer
• 16-Bit Synchronous Counter
• 16-Bit Asynchronous Counter
In Synchronous Timer configuration, the timer is
clocked by the internal device clock. The optional
Timer5 prescaler divides the input by 2, 4, 8 or not at all
(1:1). The TMR5 register pair increments on Q1.
Clearing TMR5CS (= 0) selects the internal device
clock as the timer sampling clock.
DS39616C-page 148
Preliminary
© 2007 Microchip Technology Inc.