PIC18F2331_07 Datasheet, PDF (70/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 50, 60
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000 50, 60
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000 50, 60
STKPTR
STKFUL STKUNF
—
SP4
SP3
SP2
SP1
SP0
00-0 0000 50, 61
PCLATU
—
—
bit 21⁽³⁾ Holding Register for PC<20:16>
---0 0000 50, 62
PCLATH
Holding Register for PC<15:8>
0000 0000 50, 62
PCL
TBLPTRU
PC Low Byte (PC<7:0>)
—
—
bit 21⁽³⁾ Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
0000 0000
--00 0000
50, 62
50, 80
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 50, 80
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 50, 80
TABLAT
Program Memory Table Latch
0000 0000 50, 80
PRODH
Product Register High Byte
xxxx xxxx 50, 91
PRODL
Product Register Low Byte
xxxx xxxx 50, 91
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF 0000 000x 50, 95
INTCON2
RBPU INTEDG0 INTEDG1 INTEDG2
—
TMR0IP
—
RBIP 1111 -1-1 50, 96
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF 11-0 0-00 50, 97
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
50, 73
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
50, 73
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
50, 73
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
50, 73
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register)
N/A
50, 73
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- xxxx 50, 73
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 50, 73
WREG
Working Register
xxxx xxxx
50
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
50, 73
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
50, 73
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
50, 73
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
50, 73
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register)
N/A
50, 73
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte ---- 0000 51, 73
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 51, 73
BSR
—
—
—
—
Bank Select Register
---- 0000 51, 72
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
51, 73
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
51, 73
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
51, 73
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
51, 73
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register)
N/A
51, 73
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte ---- 0000 51, 73
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx 51, 73
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx 51, 75
TMR0H
Timer0 Register High Byte
0000 0000 51, 137
TMR0L
Timer0 Register Low Byte
xxxx xxxx 51, 137
T0CON
TMR0ON T016BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0 1111 1111 51, 135
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented.
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
‘0’ in all other oscillator modes.
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
If PBADEN = 0, PORTB<4:0> are configured as digital inputs and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as
analog inputs and read ‘0’ following a Reset.
These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’.
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3 reads ‘0’. This bit is read-only.
DS39616C-page 68
Preliminary
© 2007 Microchip Technology Inc.