PIC18F2331_07 Datasheet, PDF (199/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 17-14:
DUTY CYCLE UPDATE TIMES IN CONTINUOUS UP/DOWN COUNT MODE WITH
DOUBLE UPDATES
Duty Cycle Value Loaded from Buffer Register
PWM Output
PTMR Value
New Values Written to Duty Cycle Buffer
17.6.4 CENTER-ALIGNED PWM
Center-aligned PWM signals are produced by the
module when the PWM time base is configured in a
Continuous Up/Down Count mode (see Figure 17-15).
The PWM compare output is driven to the active state
when the value of the Duty Cycle register matches the
value of PTMR and the PWM time base is counting
downwards (PTDIR = 1). The PWM compare output
will be driven to the inactive state when the PWM time
base is counting upwards (PTDIR = 0) and the value in
the PTMR register matches the duty cycle value. If the
value in a particular Duty Cycle register is zero, then
the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the
output on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is equal to
or greater than the value in the PTPER register.
Note:
When the PWM is started in
Center-Aligned mode, the PWM Time
Base Period register (PTPER) is loaded
into the PWM Time Base register (PTMR)
and the PTMR is configured automatically
to start down counting. This is done to
ensure that all the PWM signals don’t start
at the same time.
FIGURE 17-15: START OF CENTER-ALIGNED PWM
PTPER
Duty
Cycle
PTMR
Value
Period/2
0
Start of
first
PWM
period
Duty Cycle
Period
Period
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 197