PIC18F2331_07 Datasheet, PDF (14/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
FIGURE 1-1:
PIC18F2331/2431 BLOCK DIAGRAM
Data Bus<8>
21
21
Address Latch
Program
Memory
Data Latch
16
21 ^{Table Pointer<21>}
inc/dec logic
8
8
20
PCLATU PCLATH
PCU PCH PCL
Program Counter
31 Level Stack
Data Latch
Data RAM
(768 bytes)
Address Latch
12
Address<12>
4
BSR
12
FSR0
FSR1
FSR2
4
Bank 0, F
12
Table Latch
8
ROM Latch
Decode
inc/dec
logic
PORTA
PORTB
PORTC
OSC2/CLKO
OSC1/CLKI
T1OSI
T1OSO
MCLR/VPP
VDD, VSS
Instruction
Decode &
Control
Timing
Generation
4X PLL
Precision
Band Gap
Reference
IR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Power-Managed
Mode Logic
INTRC
OSC
8
PRODH PRODL
3
8 x 8 Multiply
8
BITOP
W
8
8
8
8
ALU<8>
8
PORTE
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CAP1/INDX
RA3/AN3/VREF+/CAP2/QEA
RA4/AN4/CAP3/QEB
OSC2/CLKO/RA6
OSC1/CLKI/RA7
RB0/PWM0
RB1/PWM1
RB2/PWM2
RB3/PWM3
RB4/KBI0/PWM5
RB5/KBI1/PWM4/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2/FLTA
RC2/CCP1/FLTB
RC3/T0CKI/T5CKI/INT0
RC4/INT1/SDI/SDA
RC5/INT2/SCK/SCL
RC6/TX/CK/SS
RC7/RX/DT/SDO
MCLR/VPP/RE3^(1,2)
Timer0
Timer1
Timer2
Timer5
HS 10-Bit
ADC
AVDD, AVSS
Data EE
CCP1
CCP2
Synchronous
Serial Port
EUSART
PCPWM
MFM
Note 1: RE3 input pin is only enabled when MCLRE fuse is programmed to ‘0’.
2: RE3 is available only when MCLR is disabled.
DS39616C-page 12
Preliminary
© 2007 Microchip Technology Inc.