PIC18F2331_07 Datasheet, PDF (30/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
2.7 Clock Sources and Oscillator
Switching
Like previous PIC18 devices, the PIC18F2331/2431/
4331/4431 devices include a feature that allows the sys-
tem clock source to be switched from the main oscillator
to an alternate low-frequency clock source. PIC18F2331/
2431/4331/4431 devices offer two alternate clock
sources. When enabled, these give additional options for
switching to the various power-managed operating
modes.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator block
The primary oscillators include the External Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mode is defined on POR by the contents
of Configuration Register 1H. The details of these
modes are covered earlier in this chapter.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC18F2331/2431/4331/4431 devices offer only the
Timer1 oscillator as a secondary oscillator. This
oscillator, in all power-managed modes, is often the
time base for functions such as a Real-Time Clock
(RTC).
Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO and RC1/T1OSI pins. Like
the LP mode oscillator circuit, loading capacitors are
also connected from each pin to ground.
The Timer1 oscillator is discussed in greater detail in
Section 12.2 “Timer1 Oscillator”.
In addition to being a primary clock source, the internal
oscillator block is available as a power-managed
mode clock source. The INTRC source is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.
The clock sources for the PIC18F2331/2431/4331/4431
devices are shown in Figure 2-8. See Section 12.0
“Timer1 Module” for further details of the Timer1
oscillator. See Section 22.1 “Configuration Bits” for
Configuration register details.
2.7.1 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several
aspects of the system clock’s operation, both in full
power operation and in power-managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source that is used when the device is operating
in power-managed modes. The available clock sources
are the primary clock (defined in Configuration Register
1H), the secondary clock (Timer1 oscillator) and the
internal oscillator block. The clock selection has no
effect until a SLEEP instruction is executed and the
device enters a power-managed mode of operation.
The SCS bits are cleared on all forms of Reset.
The Internal Oscillator Select bits, IRCF2:IRCF0, select
the frequency output of the internal oscillator block that
is used to drive the system clock. The choices are the
INTRC source, the INTOSC source (8 MHz) or one of
the six frequencies derived from the INTOSC
postscaler (125 kHz to 4 MHz). If the internal oscillator
block is supplying the system clock, changing the
states of these bits will have an immediate change on
the internal oscillator’s output.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the system clock. The OSTS
indicates that the Oscillator Start-up Timer has timed out,
and the primary clock is providing the system clock in
primary clock modes. The IOFS bit indicates when the
internal oscillator block has stabilized, and is providing
the system clock in RC Clock modes. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
providing the system clock in secondary clock modes. In
power-managed modes, only one of these three bits will
be set at any time. If none of these bits are set, the INTRC
is providing the system clock, or the internal oscillator
block has just started and is not yet stable.
The IDLEN bit controls the selective shutdown of the
controller’s CPU in power-managed modes. The use of
these bits is discussed in more detail in Section 3.0
“Power-Managed Modes”
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control
register (T1CON<3>). If the Timer1
oscillator is not enabled, then any attempt
to select a secondary clock source when
executing a SLEEP instruction will be
ignored.
2: It is recommended that the Timer1
oscillator be operating and stable before
executing the SLEEP instruction, or a very
long delay may occur while the Timer1
oscillator starts.
DS39616C-page 28
Preliminary
© 2007 Microchip Technology Inc.