PIC18F2331_07 Datasheet, PDF (243/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
19.4.2 EUSART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>) or the Continuous Receive Enable
bit, CREN (RCSTA<4>). Data is sampled on the RC7/
RX/DT/SDO pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. Ensure bits, CREN and SREN, are clear.
4. If interrupts are desired, set enable bit, RCIE.
5. If 9-bit reception is desired, set bit, RX9.
6. If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
7. Interrupt flag bit, RCIF, will be set when
reception is complete and an interrupt will be
generated if the enable bit, RCIE, was set.
8. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT/SDO
Pin
RC6/TX/CK/SS
Pin
(SCKP = 0)
RC6/TX/CK/SS
Pin
(SCKP = 1)
Write to
bit SREN
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
SREN bit
CREN bit ‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 19-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1
—
ADIF
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
PIE1
—
ADIE
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
IPR1
—
ADIP
RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP -111 1111 -111 1111
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
RCREG EUSART Receive Register
0000 0000 0000 0000
TXSTA
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
BAUDCTL
—
RCIDL
—
SCKP BRG16
—
WUE ABDEN -1-1 0-00 -1-1 0-00
SPBRGH EUSART Baud Rate Generator Register High Byte
0000 0000 0000 0000
SPBRG EUSART Baud Rate Generator Register Low Byte
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 241