PIC18F2331_07 Datasheet, PDF (51/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
4.6 Time-out Sequence
On power-up, the time-out sequence is as follows:
First, after the POR pulse has cleared, PWRT time-out
is invoked (if enabled). Then, the OST is activated. The
total time-out will vary based on oscillator configuration
and the status of the PWRT. For example, in RC mode
with the PWRT disabled, there will be no time-out at all.
Figures 4-3 through 4-7 depict time-out sequences on
power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bring-
ing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
Table 4-2 shows the Reset conditions for some Special
Function Registers, while Table 4-3 shows the Reset
conditions for all the registers.
TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up⁽²⁾ and Brown-out
PWRTEN = 0
PWRTEN = 1
HSPLL
HS, XT, LP
EC, ECIO
RC, RCIO
INTIO1, INTIO2
66 ms⁽¹⁾ + 1024 TOSC + 2 ms⁽²⁾
66 ms⁽¹⁾ + 1024 TOSC
66 ms⁽¹⁾
66 ms⁽¹⁾
66 ms⁽¹⁾
1024 TOSC + 2 ms⁽²⁾
1024 TOSC
—
—
—
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the 4x PLL to lock.
Exit From
Power-Managed Mode
1024 TOSC + 2 ms⁽²⁾
1024 TOSC
—
—
—
REGISTER 4-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
U-0
U-0
R/W-1
R-1
R-1
IPEN
—
—
RI
TO
PD
bit 7
Note: Refer to Section 5.14 “RCON Register” for bit definitions.
R/W-0
POR
R/W-0
BOR
bit 0
TABLE 4-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program RCON
Counter Register
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
RESET Instruction
Brown-out
0000h 0--1 1100 1 1 1 0
0
0
0
0000h 0--0 uuuu 0 u u u
u
u
u
0000h 0--1 11u- 1 1 1 u
0
u
u
MCLR Reset during power-managed
0000h 0--u 1uuu u 1 u u
u
u
u
Run modes
MCLR Reset during power-managed Idle 0000h 0--u 10uu u 1 0 u
u
u
u
and Sleep modes
WDT Time-out during full power or
power-managed Run modes
0000h 0--u 0uuu u 0 u u
u
u
u
MCLR Reset during full power execution
u
u
Stack Full Reset (STVREN = 1)
0000h 0--u uuuu u u u u
u
1
u
Stack Underflow Reset (STVREN = 1)
u
1
Stack Underflow Error (not an actual
0000h u--u uuuu u u u u
u
u
1
Reset, STVREN = 0)
WDT time-out during power-managed Idle PC + 2 u--u 00uu u 0 0 u
u
u
u
or Sleep modes
Interrupt exit from power-managed modes PC + 2⁽¹⁾ u--u u0uu u u 0
u
u
u
u
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’.
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
© 2007 Microchip Technology Inc.
Preliminary
DS39616C-page 49