PIC18F2331_07 Datasheet, PDF (142/400 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D

PIC18F2331/2431/4331/4431
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the Timer1 Clock
Select bit, TMR1CS (T1CON<1>).
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2/FLTA and RC0/T1OSO/
T1CKI pins become inputs. That is, the
TRISC1:TRISC0 value is ignored and the pins are read
as ‘0’.
Timer1 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
Section 15.4.4 “Special Event Trigger”).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
TMR1IF
Overflow
Interrupt
Flag Bit
T1CKI/T1OSO
T1OSI
CCP Special Event Trigger
TMR1
CLR
TMR1H TMR1L
T1OSC
T1OSCEN
Enable
Oscillator⁽¹⁾
Synchronized
0
Clock Input
TMR1ON
On/Off
1
T1SYNC
FOSC/4
Internal
Clock
1
Prescaler
1, 2, 4, 8
0
2
T1CKPS1:T1CKPS0
TMR1CS
Synchronize
det
Peripheral Clocks
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag bit
T1CKI/T1OSO
T1OSI
8
TMR1
Timer1
High Byte
CLR
TMR1L
T1OSC
TMR1ON
On/Off
1
T1OSCEN
Enable
Oscillator⁽¹⁾
FOSC/4
Internal 0
Clock
0
1
T1SYNC
Prescaler
1, 2, 4, 8
2
TMR1CS
T1CKPS1:T1CKPS0
Synchronized
Clock Input
Synchronize
det
Peripheral Clocks
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39616C-page 140
Preliminary
© 2007 Microchip Technology Inc.